Senior SoC Verification Architect

T-FOOTPRINT; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

T-FOOTPRINT in Bayan Lepas, Penang, is seeking a Design Verification Engineer with 3+ years of experience to verify IP blocks and SoC designs, develop verification environments, and collaborate with cross-functional teams to debug complex design issues.

You will build and execute verification plans, create UVM-based testbenches, and contribute to system-level validation, ensuring functional correctness and design quality across modules.

Qualifications

• Degree in Electrical/Electronics/Computer Engineering or related field.
• Strong understanding of digital design and verification methodologies.
• Proficiency in C programming for test cases and verification utilities.
• Experience with functional, interface, and/or SoC-level verification.
• Strong debugging and problem-solving skills to resolve complex verification issues.
• Excellent communication and collaboration skills.

Responsibilities

• Verify IP blocks and SoC designs and ensure functional correctness.
• Develop and execute verification plans, test scenarios, and test cases.
• Develop and maintain UVM-based verification environments, testbenches, and verification infrastructure.
• Perform functional, interface, performance, and system-level verification, including debugging and root-cause analysis.
• Support IP integration and SoC verification with cross-functional teams.
• Identify, analyze, and resolve verification issues to ensure design quality.

Skills

Digital design

Verification methodologies

C programming

SoC verification

Debugging skills

Team collaboration

Education

Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering, or related field

Job description

T-FOOTPRINT in Bayan Lepas, Penang, is seeking a Design Verification Engineer with 3+ years of experience to verify IP blocks and SoC designs, develop verification environments, and collaborate with cross-functional teams to debug complex design issues.

You will build and execute verification plans, create UVM-based testbenches, and contribute to system-level validation, ensuring functional correctness and design quality across modules.