Senior Physical Design Engineer - RTL to GDSII and Tapeout

Alchip Technologies; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

Alchip Technologies in Penang is seeking a backend IC design engineer to drive RTL-to-GDSII implementation for block-level or full-chip SoCs. You will work closely with front-end teams to ensure physical feasibility and optimize PPA for timing and congestion.

The role requires a degree in EE and hands-on experience with tapeout, Tcl/Perl scripting, and standard EDA tools. You will manage backend schedules and lead risk mitigation efforts in a fast-paced environment.

Qualifications

• Bachelor's or MS degree in EE or related field.
• Experience with top-level design and chip floorplanning.
• Familiar with Cadence EDI, Synopsys ICC flow and Mentor Calibre.

Responsibilities

• Implement RTL-to-GDSII flow for block-level or full-chip SoCs.
• Coordinate with front-end design team to ensure design feasibility.
• Analyze backend timing, congestion, and optimize PPA from an implementation view.
• Perform sign-off tasks such as STA/IR/EM/PV, etc.
• Lead backend status tracking, identify risks, and drive risk mitigation.

Skills

Top-level design experience

Chip floorplan experience

Design automation

PPA optimization

Scripting (Tcl/Perl)

Education

Bachelor's or MS in EE or related

Tools

Cadence EDI

Synopsys ICC design flow

Mentor Calibre

Job description

Alchip Technologies in Penang is seeking a backend IC design engineer to drive RTL-to-GDSII implementation for block-level or full-chip SoCs. You will work closely with front-end teams to ensure physical feasibility and optimize PPA for timing and congestion.

The role requires a degree in EE and hands-on experience with tapeout, Tcl/Perl scripting, and standard EDA tools. You will manage backend schedules and lead risk mitigation efforts in a fast-paced environment.