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Private Advertiser seeks an IC design engineer with 3+ years of experience to work on full-chip projects in a multinational Penang environment.
You will contribute to either digital frontend RTL design or backend physical design, coordinating with verification, DFT, layout, and foundry teams to ensure stable, tapeout-ready designs and post-silicon optimization.
You will participate in the full-chip design cycle, covering either digital frontend RTL design or backend physical design for SoC/IP projects. You will collaborate with verification, DFT, layout, and foundry teams to deliver high-quality, stable, and tapeout-ready semiconductor designs, and support post-silicon validation and technical optimization.
Key responsibilities
Understand project specifications, architecture requirements, and design constraints, complete module-level and top-level RTL design and coding using Verilog/SystemVerilog
Cooperate with DV verification team to resolve functional bugs, optimize code structure, and ensure design testability and reusability
Work with DFT engineers to insert scan, JTAG, and test logic, and support DFT implementation
Complete design documentation, including design specification, design guide, and release checklist
Responsible for full backend physical design flow: floorplan, power planning, placement, CTS, routing, timing closure, and physical signoff
Perform static timing analysis (STA), fix setup/hold violations, optimize timing, power and area (PPA)
Complete physical verification including DRC, LVS, ERC, ensure design complies with foundry process rules
Collaborate with frontend design team to handle ECO changes, resolve timing and physical implementation issues
Follow semiconductor design standard flow and methodology, maintain design quality and project schedule
About you
Bachelor or Master degree in Electrical Engineering, Electronics, Microelectronics, Computer Engineering or related fields
3+ years of IC design experience
Proficient in Verilog/SystemVerilog, familiar with RTL coding style, simulation environment, basic timing concept and SOC design flow
Familiar with industry-standard physical design flow, proficient in floorplan, placement, CTS, routing, STA timing closure and signoff checks
Familiar with EDA tools (Synopsys / Cadence flow)
Good understanding of semiconductor process, timing, power and area constraints
Good English reading and communication skills, able to work in a multinational team environment
Responsible, careful, able to work under project schedule pressure
Competitive salary + performance bonus
Professional IC design training and technical growth path
Multinational working environment in Penang E&E semiconductor hub