Senior IC/SoC Physical Design Engineer | End-to-End Tapeout

UST Malaysia; Seberang Perai; Sur place; MYR 200 000 - 280 000; Plein temps

Résumé du poste

UST Malaysia seeks a Senior Physical Design Engineer with 8+ years of ASIC/SoC experience to lead full-chip and block-level physical design, including floorplanning, CTS, routing and timing closure for advanced nodes.

You will collaborate with RTL, DFT, STA and Verification teams to achieve design closure while optimizing area, power, and performance. You will also support tapeout and silicon bring-up, mentoring junior engineers along the way.

Qualifications

• 8+ years of hands-on experience in ASIC/SoC Physical Design.

Responsabilités

• Perform end-to-end Physical Design implementation from netlist to GDSII.
• Drive Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Analyze and close timing, congestion, power, signal integrity, and DRC/LVS issues.
• Collaborate with RTL, DFT, STA, and Verification teams to achieve design closure.
• Optimize area, power, and performance (PPA) targets.
• Support tapeout activities and silicon bring-up.

Connaissances

Floorplanning

Power Planning

Placement & Optimization

CTS

Timing Closure

Routing

Physical Verification

IR Drop

EM

Signal Integrity

Scripting (Tcl/Perl/Python)

Formation

Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering

Outils

Cadence Innovus

Synopsys ICC2/Fusion Compiler

PrimeTime

Calibre

Description du poste

UST Malaysia seeks a Senior Physical Design Engineer with 8+ years of ASIC/SoC experience to lead full-chip and block-level physical design, including floorplanning, CTS, routing and timing closure for advanced nodes.

You will collaborate with RTL, DFT, STA and Verification teams to achieve design closure while optimizing area, power, and performance. You will also support tapeout and silicon bring-up, mentoring junior engineers along the way.