Senior ASIC Design Architect: RTL to Tapeout

Microchip Technology Inc.; Penang; Presencial; MYR 180.000 - 280.000; Jornada completa

Descripción de la vacante

FHLB Des Moines is seeking an experienced ASIC design lead in Penang to drive from RTL to GDS implementation and tapeout readiness. You will work on timing signoffs, DFT, and low-power optimization while guiding team members through complex challenges.

The ideal candidate has 12–16 years of ASIC IC design experience, proficiency with Cadence and Synopsys tools, SystemVerilog, and scripting skills across Perl/TCL/Shell/Python. Travel up to 25% may be required.

Formación

• Bachelor’s or Master’s Degree in Electrical/Electronics Engineering.
• Expertise in Cadence Genus or Synopsys DesignCompiler.
• Expertise in Cadence Tempus or Synopsys PrimeTime.
• Exposure to 7nm and below process nodes.
• Familiarity with System-Verilog.
• Strong scripting in Perl, TCL, Shell or Python.
• Travel 0% – 25%.

Responsabilidades

• Lead technically in ASIC design implementation from RTL to GDS for tapeout readiness.
• Derive timing constraints and obtain signoff with designers.
• Implement DFT, including scan insertion and related techniques.
• Optimize low-power design through architectural feedback and layout/synthesis improvements.
• Provide guidance and review for team members on complex design challenges.

Conocimientos

SystemVerilog knowledge

Scripting skills

ASIC IC design

Educación

Bachelor's or Master's in Electrical/Electronics Engineering

Herramientas

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys PrimeTime

Descripción del empleo

FHLB Des Moines is seeking an experienced ASIC design lead in Penang to drive from RTL to GDS implementation and tapeout readiness. You will work on timing signoffs, DFT, and low-power optimization while guiding team members through complex challenges.

The ideal candidate has 12–16 years of ASIC IC design experience, proficiency with Cadence and Synopsys tools, SystemVerilog, and scripting skills across Perl/TCL/Shell/Python. Travel up to 25% may be required.