Physical Design Engineer - RTL to GDS, Power & Timing

Altera; George Town; On-site; MYR 60,000 - 90,000; Full time

Job summary

Altera in Penang, Malaysia is seeking a hands-on Physical Design Engineer to implement IPs and SoCs from RTL to GDS. You will drive synthesis, place-and-route, STA, clocking, power integrity and signoff, delivering robust design databases for manufacturing.

The role requires 3+ years in physical design, scripting (Perl/TCL/Python), and experience with VHDL/Verilog; mentoring teammates and improving design methodologies are valued.

Qualifications

• Bachelor's degree in computer engineering, electronic Engineering or related field.
• 3+ years of relevant experience in physical design flow and EDA tools, with multiple tape-out experience in deep submicron nodes.
• Hands-on scripting with Perl, TCL, Python; HDL knowledge of VHDL and Verilog.

Responsibilities

• Perform physical design implementation of IP and SoC designs from RTL to GDS to create manufacturable design databases.
• Conduct synthesis, place-and-route, clock tree synthesis, floor planning, STA, PDS, power/clock distribution, reliability and noise analysis; signoff activities.
• Mentor junior team members and contribute to flow automation and design methodology improvements.

Skills

Mentoring

Analytical thinking

Teamwork

Multitasking

Education

Bachelor's degree in Computer/Electronic Engineering

Tools

Perl

TCL

Python

VHDL

Verilog

Job description

Altera in Penang, Malaysia is seeking a hands-on Physical Design Engineer to implement IPs and SoCs from RTL to GDS. You will drive synthesis, place-and-route, STA, clocking, power integrity and signoff, delivering robust design databases for manufacturing.

The role requires 3+ years in physical design, scripting (Perl/TCL/Python), and experience with VHDL/Verilog; mentoring teammates and improving design methodologies are valued.