Senior Physical Design Engineer (PnR)

UST Malaysia; Penang; On-site; MYR 120,000 - 300,000; Full time

Job summary

UST Malaysia is seeking a Senior Physical Design Engineer with 8+ years of ASIC/SoC experience to lead full-chip and block-level PD in Penang. You will drive floorplanning, placement, CTS, routing, timing closure and physical signoff for advanced nodes.

Work with RTL, DFT, STA and verification teams to achieve design closure while optimizing area, power and performance and supporting tapeout and silicon bring-up.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• 8+ years hands-on ASIC/SoC Physical Design experience.
• Expertise in Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Proficiency with Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, and Calibre.

Responsibilities

• Lead end-to-end Physical Design from netlist to GDSII.
• Drive floorplanning, power planning, placement, CTS, routing, and signoff.
• Analyze timing, congestion, power, SI, and DRC/LVS issues.
• Collaborate with RTL, STA, DFT, and verification teams to close design.

Skills

ASIC/SoC PD

Floorplanning

Power Planning

Placement & Optimization

CTS

Timing Closure

Routing

Physical Verification

Scripting (Tcl/Python)

Collaboration

Education

Bachelor's or Master's in Electrical/Electronics/CE

Tools

Cadence Innovus

Synopsys ICC2/Fusion Compiler

PrimeTime

Calibre

Job description

We are seeking a Senior Physical Design Engineer with 8+ years of experience in ASIC/SoC implementation. The ideal candidate will have strong expertise in full-chip and block-level Physical Design, including Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, Timing Closure, and Physical Signoff for advanced technology nodes.

Key Responsibilities

• Perform end-to-end Physical Design implementation from netlist to GDSII.
• Drive Floorplanning, Power Planning, Placement, CTS, Routing, and Physical Verification.
• Analyze and close timing, congestion, power, signal integrity, and DRC/LVS issues.
• Collaborate with RTL, DFT, STA, and Verification teams to achieve design closure.
• Optimize area, power, and performance (PPA) targets.
• Support tapeout activities and silicon bring-up.

Required Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering.
• 8+ years of hands-on experience in ASIC/SoC Physical Design.
• Strong expertise in: Floorplanning, Power Planning, Placement & Optimization, CTS and Timing Closure, Routing and Physical Verification, IR Drop, EM, and Signal Integrity analysis
• Experience with industry-standard EDA tools such as: Cadence Innovus, Synopsys ICC2/Fusion Compiler, PrimeTime, Calibre
• Strong understanding of advanced technology nodes (16nm and below preferred).
• Proficiency in Tcl, Perl, or Python scripting.

Preferred Qualifications

• Experience with full-chip integration and tapeout.
• Knowledge of low-power design methodologies (UPF/CPF).
• Exposure to AI/HPC, Networking, Mobile, or Automotive SoCs.
• Experience in advanced nodes such as 7nm, 5nm, or below.

Key Skills

• Excellent timing and physical closure debugging skills.
• Strong analytical and problem-solving abilities.
• Effective communication and cross-functional collaboration.
• Ability to mentor junior engineers and drive project deliverables independently.