Senior Full-Chip CPU Physical Design Engineer (Hybrid)

Intel Corporation; George Town; Hybrid; MYR 180,000 - 300,000; Full time

Benefits offered by this job

Hybrid work model

Job summary

Intel Corporation seeks an experienced Full-Chip design engineer to drive floorplanning, pin and feedthrough planning, and multi-project convergence for a high-frequency CPU integration. You will coordinate with back-end groups to ensure robust physical design and timing closure while improving FC methodology.

The role requires leadership to run multiple projects in parallel, strong communication, and hands-on use of EDA tools for optimization, reliability checks, and integration of partitions.

Qualifications

• BS or MS in Electrical Engineering or Computer Engineering.
• Minimum 7 years of CPU physical design and timing verification experience.
• Experience with Fusion Compiler, RedHawk, ICV, Conformal, Calibre, PrimeTime, StarRCXT is a plus.

Responsibilities

• Perform floorplanning, pin and feedthrough planning, repeater insertion, power grid generation, and partition assembly.
• Drive FC methodology efficiency, including floorplan optimization for QoR and timing.
• Coordinate collateral handoffs between FC Design and back-end functions (Clocking, Power Delivery, APR).
• Drive physical design and timing closure (FEV, LVS, DRC, reliability verification such as IR drop/EM).

Skills

CPU physical design

Timing verification

Tcl scripting

Noise analysis

Cross-talk analysis

Floorplanning

Timing closure

DRC/LVS checks

Electro-migration checks

Education

BS or MS in Electrical Engineering or Computer Engineering

Tools

Fusion Compiler

RedHawk

ICV

Conformal

Calibre

PrimeTime

StarRCXT

Job description

Intel Corporation seeks an experienced Full-Chip design engineer to drive floorplanning, pin and feedthrough planning, and multi-project convergence for a high-frequency CPU integration. You will coordinate with back-end groups to ensure robust physical design and timing closure while improving FC methodology.

The role requires leadership to run multiple projects in parallel, strong communication, and hands-on use of EDA tools for optimization, reliability checks, and integration of partitions.