Custom Layout Engineer

AdoreSys; Bayan Lepas; In loco; MYR 90.000 - 150.000; Tempo pieno

Descrizione del lavoro

AdoreSys is seeking Custom Layout Engineers (Junior to Technical Lead) in Bayan Lepas, Penang, Malaysia, to drive the physical implementation of advanced IC designs.

The role covers floorplanning, layout construction, and verification across Standard Cell, Memory Compiler, and IO/ESD libraries, with emphasis on PPA optimization and multi-team coordination.

Competenze

• 2–7 years of hands-on custom IC layout experience.
• Experience with Standard Cell, Memory Compiler or IO/ESD libraries preferred.
• Strong understanding of DRM, deep sub-micron and DFM for high-performance layouts.
• Proficient in debugging DRC/LVS/ERC checks.

Mansioni

• Realize physical implementation of diverse circuitry including Foundation IP, Analog IP, and RF building blocks.
• Lead floorplanning, layout construction, and physical verification with QA flow sign-off.
• Provide timely project updates and mitigate risks to ensure on-time delivery.
• Collaborate with cross-site teams to optimize layout for Power, Performance & Area (PPA).

Conoscenze

Layout debugging

DRM knowledge

DFM considerations

Team collaboration

Formazione

Bachelor's degree in Electrical, Electronic, or Material Science Engineering

Strumenti

Synopsys/Cadence layout editor

Physical verification tools

Descrizione del lavoro

Level: Junior/Senior/Staff/Technical Lead

Overview:

Are you passionate about driving innovation in microchip design? Ready to take the lead in shaping the next generation of integrated circuits? We’re looking for a variety of positions for Custom Layout Engineer to join our team and make a significant impact on advanced semiconductor technology—including the chips powering tomorrow’s AI breakthroughs.

What you’ll do:

• Undertake the roles of a custom layout engineer in realizing the physical implementation of a variety of circuitries, including Foundation IP (Standard Cells, Memory Compilers, IO/ESD), Analog IP, and RF building blocks.
• Be responsible for tasks assigned and assume full responsibility of the complete layout implementation process, including floorplanning, layout construction, physical verification and QA flow sign-off.
• Provide timely project status updates and proactively anticipate potential execution pitfalls to ensure high-quality and on-time delivery for each project.
• Be proactive in communicating effectively with multi-functional teams and multi-site to constantly optimize layout for better Power, Performance & Area (PPA).

Who we’re looking for:

• Bachelor’s degree in Electrical, Electronic, or Material Science Engineering.
• More than 2~7 years of hands-on experience in custom IC layout for Standard Cell, Memory Compiler or IO/ESD libraries using advanced finFET/GAA process nodes; candidates with Analog/RF experiences are welcomed to apply.
• Proficient in understanding DRM of advanced CMOS technologies and have a good grasp of deep sub-micron and DFM issues for high-performance layout designs.
• Analytical and skillful in debugging physical verification checks (eg. DRC/LVS/ERC, etc.).
• Proficient in Synopsys/Cadence layout editor and physical verification tools.
• Team player and effective in cross-team communication and time management.
• Experienced candidate will be considered for senior position.