Senior Physical Design Engineer

UST; Bayan Lepas; On-site; MYR 160,000 - 230,000; Full time

Job summary

UST is seeking a Physical Design Engineer (PnR or STA) to own full-custom analog and mixed-signal layout in deep submicron FinFET tech. You will handle placement, routing, DRC/STA, PI, DFM/DFR checks, and data delivery in a collaborative team.

The role requires expertise in floor planning, ECO generation for timing/noise/EMIR, and proficiency with Tcl/Perl/Python, plus Cadence/Synopsys/Mentor tools and Calibre for DRC/LVS/PERC verification.

Qualifications

• Experience in synthesis, Place & Route, timing closure, PV, PI, PPA improvement.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below); FinFET.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts; Generating and implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching.
• Knowledge of LEF and DEF of analog/custom blocks, integrate into P&R database, and merge into Cadence Virtuoso.
• Strong digital CMOS knowledge; deep understanding of semiconductor process and device physics.
• Good learning competency, self-motivated, and able to work in diverse areas in a flexible environment.
• At least 6 years of relevant experience.
• Bachelor of Engineering or ME/M.Tech

Responsibilities

• Perform full-custom analog and mixed-signal layout in a team environment.
• Deliver physical design data with proper verification and timing closure.
• Maintain hierarchy for extraction and verification; merge databases into Cadence Virtuoso.
• Ensure power grid design meets EMIR requirements and supports high-speed interfaces.

Skills

Place & Route

Timing closure

PV/PI

PPA improvement

Synthesis

Floor planning

ECOs (timing/noise/EMIR)

Programming (Tcl/Perl/Python)

Calibre DRC/LVS/PERC

CMOS/digital & analog layout

Education

Bachelor of Engineering or ME/M.Tech

Tools

Cadence

Synopsys

Mentor

Calibre

Totem EM & IR analysis

Job description

Physical Design Engineer (PnR or STA)

Responsible for all aspects of Physical design (Place & Route, DRC STA analysis, PI/SI analysis, physical verification, DFR design and verification, DFM design and verification, physical design data delivery.), Full custom and its implementation in a team environment performing full-custom analog and mixed-signal layout of next generation high-speed interfaces and signal integrity systems (aka SerDes, PHY) in deep submicron FinFET technologies.

Job Requirements:

• Experienced in synthesis, Place & Route, timing closure, PV, PI, PPA improvement. etc and major EDA tools including Cadence, Synopsys, and Mentor tools.
• Implementation of multimillion gate SoC designs in cutting edge process technologies (16nm,14nm & below). Experience in Finfet technologies is a must.
• Expertise in floor planning including power grid design to meet EMIR specifications.
• Good understanding of timing concepts, Experience in Generating and Implementing ECOs to fix timing, noise, and EMIR violations.
• Experience in Tcl/Perl/Shell/Python programming, Mentor Calibre DRC/LVS/PERC, and Apache Totem EM & IR analysis is a plus.
• Familiar with mixed signal layout matching techniques, such as interdigitation, common centroid and dummies for matching, bypass capacitor design and optimization, power supply bus construction using star connections, critical route shielding, triple well layout, ESD device and cell layout, and guard ring layout methods.
• Knowledge of low-power UPF flows. Ability to create LEF and DEF of analog/custom blocks, define the pins ports for the block, integrate them into the P&R database, and maintain the hierarchy for extraction and verification. Need to be able to merge and integrate the database into the Cadence Virtuoso database.
• Good understanding of advanced semiconductor technology process and device physics. Strong in digital logic design, CMOS & strong analytical ability.
• Good learning competency, self-motivated, and ability to work in diverse areas in a flexible and dynamic environment
• At least 6 years of relevant experience
• Bachelor of Engineering or ME/M.Tech