Senior PCIe Verification Engineer (SystemVerilog/UVM)

UST; Penang; On-site; MYR 70,000 - 110,000; Full time

Job summary

UST in Penang, Malaysia is seeking a verification engineer to develop and execute verification plans for PCIe IP/SoC designs. The role includes building SystemVerilog/UVM environments, creating directed and constrained-random tests, and verifying PCIe Gen3/Gen4/Gen5 protocol compliance and functional correctness.

You will debug RTL, analyze waveforms, and drive verification closure while collaborating closely with design, architecture, and validation teams.

Qualifications

• Bachelor's degree in Electrical/Electronics/Computer Engineering or related field.
• Strong hands-on experience with SystemVerilog, UVM, and PCIe protocol verification.

Responsibilities

• Develop and execute verification plans for PCIe IP/SoC designs.
• Build and maintain SystemVerilog/UVM verification environments.
• Develop directed and constrained-random test cases to achieve coverage goals.
• Verify PCIe protocol (Gen3/Gen4/Gen5), including protocol compliance and functional correctness.
• Debug RTL and simulation issues, analyze waveforms, and support verification closure.
• Collaborate with design, architecture, and validation teams.

Skills

SystemVerilog

UVM

PCIe protocol verification

Education

Bachelor's degree in Electrical/Electronics/Computer Engineering or related field

Job description

UST in Penang, Malaysia is seeking a verification engineer to develop and execute verification plans for PCIe IP/SoC designs. The role includes building SystemVerilog/UVM environments, creating directed and constrained-random tests, and verifying PCIe Gen3/Gen4/Gen5 protocol compliance and functional correctness.

You will debug RTL, analyze waveforms, and drive verification closure while collaborating closely with design, architecture, and validation teams.