Senior ASIC Verification Engineer: DDR4/5 & UVM

FHLB Des Moines; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Microchip Technology Inc. in Penang, Malaysia seeks an experienced memory verification engineer to verify DDR4/DDR5 controllers and AXI interfaces for IP designs. You will develop SystemVerilog UVM environments, write constrained-random test cases, and build scoreboards and assertions to ensure data integrity.

The role requires 10+ years in SoC/IP verification, DDR protocol expertise, and hands-on with VCS/Questa/Xcelium. Strong debugging, collaboration, and leadership skills are essential.

Qualifications

• 10+ years in SoC/IP verification (memory subsystems preferred).
• Strong knowledge of DDR protocol (JEDEC).
• Hands-on with SystemVerilog, UVM, and verification methodology.

Responsibilities

• Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
• Define verification plans, design testbenches, and create directed and constrained-random testcases.
• Validate ECC, parity, and command/address/data integrity mechanisms.

Skills

SystemVerilog

UVM

DDR protocol

AXI protocol

SVA

Python scripting

Education

Bachelor's or Master in Electronics/EE/CS

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Microchip Technology Inc. in Penang, Malaysia seeks an experienced memory verification engineer to verify DDR4/DDR5 controllers and AXI interfaces for IP designs. You will develop SystemVerilog UVM environments, write constrained-random test cases, and build scoreboards and assertions to ensure data integrity.

The role requires 10+ years in SoC/IP verification, DDR protocol expertise, and hands-on with VCS/Questa/Xcelium. Strong debugging, collaboration, and leadership skills are essential.