Senior PCIe Verification Engineer

UST; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST in Penang, Malaysia seeks an experienced Design Verification Engineer to develop PCIe verification plans, build SystemVerilog/UVM based environments, and verify PCIe functionality across protocol layers. You will create testbenches, constrained-random tests, and perform coverage analysis while debugging and collaborating with design teams.

The role emphasizes verification reviews, continuous methodology improvement, and regression support.

Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, Computer Engineering, or a related field.
• 6+ years of experience in Design Verification.
• Strong experience with PCI Express (PCIe) protocol verification.
• Excellent knowledge of SystemVerilog and UVM.
• Experience with simulation/debug tools such as VCS, Xcelium, QuestaSim, or similar.
• Good understanding of digital design concepts, RTL, and verification methodologies.
• Experience with scripting languages such as Python, Perl, or Shell is an advantage.
• Strong debugging, analytical, and communication skills.

Responsibilities

• Develop and execute verification plans for PCIe IP/SoC designs.
• Create and maintain SystemVerilog/UVM-based verification environments, testbenches, and test cases.
• Verify PCIe functionality across protocol layers and ensure PCIe spec compliance.
• Develop constrained-random and directed test scenarios.
• Perform functional coverage analysis, code coverage, and assertion-based verification.
• Debug simulation failures and collaborate with design engineers to resolve issues.
• Participate in verification reviews and contribute to continuous improvement of verification methodologies.
• Support regression execution, bug tracking, and verification closure.

Skills

Debugging

Analytical thinking

Communication

Collaboration

Education

Bachelors/Masters in Electronics/EE/CE

Related field

Tools

SystemVerilog

UVM

VCS

Xcelium

QuestaSim

Python

Perl

Shell

Job description

UST in Penang, Malaysia seeks an experienced Design Verification Engineer to develop PCIe verification plans, build SystemVerilog/UVM based environments, and verify PCIe functionality across protocol layers. You will create testbenches, constrained-random tests, and perform coverage analysis while debugging and collaborating with design teams.

The role emphasizes verification reviews, continuous methodology improvement, and regression support.