Senior PCIe Verification Engineer | SystemVerilog & UVM

UST; Penang; On-site; MYR 60,000 - 120,000; Full time

Job summary

UST in Penang is seeking a Verification Engineer to develop verification plans for PCIe IP/SoC designs and to build robust SystemVerilog/UVM verification environments.

You will develop directed and constrained-random test cases to achieve coverage goals and verify PCIe protocol (Gen3/Gen4/Gen5) for protocol compliance and functional correctness. You will debug RTL, analyze waveforms, and collaborate with design, architecture, and validation teams.

Qualifications

• Bachelor's degree required in Electrical/Electronics/Computer Engineering or related field.
• Strong hands-on experience with SystemVerilog, UVM, and PCIe protocol verification.

Responsibilities

• Develop and execute verification plans for PCIe IP/SoC designs.
• Build and maintain SystemVerilog/UVM verification environments.
• Develop directed and constrained-random test cases to achieve coverage goals.
• Verify PCIe protocol (Gen3/Gen4/Gen5), including protocol compliance and functional correctness.
• Debug RTL and simulation issues, analyze waveforms, and support verification closure.
• Collaborate with design, architecture, and validation teams.

Skills

SystemVerilog

UVM

PCIe protocol verification

Education

Bachelor's degree in Electrical/Electronics/Computer Engineering or related field

Job description

UST in Penang is seeking a Verification Engineer to develop verification plans for PCIe IP/SoC designs and to build robust SystemVerilog/UVM verification environments.

You will develop directed and constrained-random test cases to achieve coverage goals and verify PCIe protocol (Gen3/Gen4/Gen5) for protocol compliance and functional correctness. You will debug RTL, analyze waveforms, and collaborate with design, architecture, and validation teams.