Senior Memory Controller Verification Engineer (UVM, DDR/LPDDR)

UST; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST in Penang, Malaysia, is seeking an experienced verification engineer for Memory Controller IPs. You will design and execute verification plans, build robust UVM environments, and create comprehensive test suites for DDR/LPDDR-based designs.

You will mentor junior engineers and collaborate across Design, Architecture, and SoC teams to improve verification methodologies. Candidates should have 6–8 years in design verification and strong exposure to VCS, Xcelium, Questa, and Verdi with AXI/AMBA

Qualifications

• 6-8 years of experience in Design Verification within the semiconductor industry.

Responsibilities

• Develop and execute verification plans for Memory Controller IPs and subsystems.
• Build and maintain verification environments using SystemVerilog and UVM.
• Create testcases, assertions, scoreboards, and coverage models.
• Perform functional, protocol, and performance verification for DDR/LPDDR-based designs.
• Debug RTL and verification issues, analyze coverage, and drive closure.
• Work closely with Design, Architecture, and SoC teams throughout the product lifecycle.
• Mentor junior verification engineers and contribute to verification methodology improvements.

Skills

UVM

Assertions (SVA)

Functional Coverage

Constrained Random Verification

AXI/AMBA protocols

Tools

VCS

Xcelium

Questa

Verdi

Job description

UST in Penang, Malaysia, is seeking an experienced verification engineer for Memory Controller IPs. You will design and execute verification plans, build robust UVM environments, and create comprehensive test suites for DDR/LPDDR-based designs.

You will mentor junior engineers and collaborate across Design, Architecture, and SoC teams to improve verification methodologies. Candidates should have 6–8 years in design verification and strong exposure to VCS, Xcelium, Questa, and Verdi with AXI/AMBA