Head of Design Verification for SoC — Strategy & Leadership

UST; Penang; On-site; MYR 180,000 - 320,000; Full time

Job summary

UST in Malaysia is seeking an experienced Design Verification Manager to lead our DV team in delivering high-quality IP and SoC products.

You will drive verification strategy, resource planning, and sign-off criteria, while mentoring engineers and ensuring timely delivery in a fast-paced environment.

Collaborate with cross-functional teams, provide technical guidance on testbenches and coverage, and help attract top DV talent.

Qualifications

• Bachelor’s or Master’s degree in EE, CE, or related field.
• 10+ years in semiconductor design verification, with 3–5 years in leadership and client liaison roles.
• Strong knowledge of verification flows, tools, and metrics (UVM, SystemVerilog, coverage-driven verification).
• Experience with PCIe, USB, DDR, Ethernet, AMBA, or other high-speed protocols.
• Familiarity with low-power verification, formal verification, or emulation.
• Proven ability to deliver multiple complex designs on schedule.
• Exceptional leadership, talent development, and communication skills.

Responsibilities

• Define and drive verification strategy, planning, and sign-off criteria for IP/SoC projects.
• Mentor and develop a high-performing DV team and drive skill growth.
• Review testbenches, assertions, and coverage models; guide complex debugging.
• Manage project priorities, schedules, resources, and risk.
• Collaborate with cross-functional teams and represent DV in program reviews.
• Identify, attract, and hire top DV talent to sustain growth.

Skills

Leadership

Mentoring

Communication

Project management

Education

Bachelor’s or Master’s in EE/CE or related field

Tools

UVM

SystemVerilog

Coverage-driven verification

Formal verification tools

Emulation

Job description

UST in Malaysia is seeking an experienced Design Verification Manager to lead our DV team in delivering high-quality IP and SoC products.

You will drive verification strategy, resource planning, and sign-off criteria, while mentoring engineers and ensuring timely delivery in a fast-paced environment.

Collaborate with cross-functional teams, provide technical guidance on testbenches and coverage, and help attract top DV talent.