Senior FPGA Timing & Silicon Integration Engineer

Lattice Semiconductor; George Town; On-site; MYR 180,000 - 250,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking a senior hardware timing engineer to collaborate across IP design and timing teams to ensure accurate FPGA timing models.

You will perform SPICE-based simulations, validate timing arcs, and bridge IP timing models with software requirements while leveraging Cadence tools and Linux scripting. Candidates with strong communication and a drive for innovation are encouraged to apply.

Qualifications

• 10 yrs experience of hardware integration design.
• Successfully went through whole development from start to Tape Out of at least 2 products.
• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
• Working knowledge of System Verilog, synthesis, and static timing analysis
• Specialist in floor-planning, power estimate, timing and back-end methodologies
• Experience with Linux scripting and Python
• Experience and knowledge of PnR is a plus
• Strong written and oral communication skills
• The ability to stay up-to-date with the latest advancements in technology & design
• Ability to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.

Responsibilities

• Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
• Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
• Perform quality checks on timing models to confirm all timing arcs meet software requirements.
• Address issues such as missing timing arcs and missing clock information.
• Generate timing reference models based on IP requirements
• Compare timing models: Current proprietary format vs. Liberty format (.lib).
• Handle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.
• Generate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.
• FPGA power model know-how and knowledge will be added advantage.
• Experience with PrimeTime/Liberate will be added advantage.

Skills

FPGA timing

Hardware integration

SystemVerilog

Python scripting

Cadence Virtuoso

SPICE simulations

Timing modeling

Synthesis & STA

Power estimation

Communication skills

Tools

PrimeTime

Liberate

Liberty format

SPICE

Job description

Lattice Semiconductor in Malaysia is seeking a senior hardware timing engineer to collaborate across IP design and timing teams to ensure accurate FPGA timing models.

You will perform SPICE-based simulations, validate timing arcs, and bridge IP timing models with software requirements while leveraging Cadence tools and Linux scripting. Candidates with strong communication and a drive for innovation are encouraged to apply.