Senior Staff FPGA Design Engineer – High-Speed Interfaces

Lattice Semiconductor; George Town; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking a Senior Staff Engineer to lead development, integration, and productization of high-speed interface subsystems for FPGA products. You will own architecture, RTL, verification, and bring-up, coordinating with hardware, software, and IP partners.

The role requires deep RTL and subsystem experience, strong debugging, and a track record of guiding complex projects from concept through silicon, with collaboration across diverse teams.

Qualifications

• Bachelor's or Master's in Electrical/Electronics/Computer Engineering.
• 15+ years in ASIC/SoC/FPGA design and product development.
• Strong RTL design and subsystem integration experience.
• Experience with AI-assisted tools and pre-silicon validation.

Responsibilities

• Lead architecture, RTL development, integration, verification, and productization of PCIe, Ethernet, USB, MIPI, SerDes, and related interfaces.
• Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, and validation.
• Drive root-cause analysis for pre-/post-silicon, software-interaction, and interoperability issues.
• Collaborate with software/firmware teams to define configuration and diagnostics.
• Engage with third-party IP suppliers to define requirements and drive technical closure.

Skills

RTL design

ASIC/FPGA

Subsystem integration

High-speed interfaces

DFT/DFD

Pre-silicon verification

Technical leadership

Stakeholder alignment

Education

Bachelor's or Master's in EE/related

Job description

Lattice Semiconductor in Malaysia is seeking a Senior Staff Engineer to lead development, integration, and productization of high-speed interface subsystems for FPGA products. You will own architecture, RTL, verification, and bring-up, coordinating with hardware, software, and IP partners.

The role requires deep RTL and subsystem experience, strong debugging, and a track record of guiding complex projects from concept through silicon, with collaboration across diverse teams.