Silicon Integration Design Engineer - Timing Model

Lattice Semiconductor; George Town; On-site; MYR 180,000 - 250,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking a senior hardware timing engineer to collaborate across IP design and timing teams to ensure accurate FPGA timing models.

You will perform SPICE-based simulations, validate timing arcs, and bridge IP timing models with software requirements while leveraging Cadence tools and Linux scripting. Candidates with strong communication and a drive for innovation are encouraged to apply.

Qualifications

• 10 yrs experience of hardware integration design.
• Successfully went through whole development from start to Tape Out of at least 2 products.
• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
• Working knowledge of System Verilog, synthesis, and static timing analysis
• Specialist in floor-planning, power estimate, timing and back-end methodologies
• Experience with Linux scripting and Python
• Experience and knowledge of PnR is a plus
• Strong written and oral communication skills
• The ability to stay up-to-date with the latest advancements in technology & design
• Ability to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.

Responsibilities

• Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
• Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
• Perform quality checks on timing models to confirm all timing arcs meet software requirements.
• Address issues such as missing timing arcs and missing clock information.
• Generate timing reference models based on IP requirements
• Compare timing models: Current proprietary format vs. Liberty format (.lib).
• Handle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.
• Generate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.
• FPGA power model know-how and knowledge will be added advantage.
• Experience with PrimeTime/Liberate will be added advantage.

Skills

FPGA timing

Hardware integration

SystemVerilog

Python scripting

Cadence Virtuoso

SPICE simulations

Timing modeling

Synthesis & STA

Power estimation

Communication skills

Tools

PrimeTime

Liberate

Liberty format

SPICE

Job description

Lattice Overview

There is energy here…energy you can feel crackling at any of our international locations. It’s an energy generated by enthusiasm for our work, for our teams, for our results, and for our customers. Lattice is a worldwide community of engineers, designers, and manufacturing operations specialists in partnership with world-class sales, marketing, and support teams, who are developing programmable logic solutions that are changing the industry. Our focus is on R&D, product innovation, and customer service, and to that focus, we bring total commitment and a keenly sharp competitive personality.

Energy feeds on energy. If you flourish in a fast paced, results-oriented environment, if you want to achieve individual success within a “team first” organization, and if you believe you can contribute and succeed in a demanding yet collegial atmosphere, then Lattice may well be just what you’re looking for.

Job Description

Detailed Description

• Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
• Understand IP functionality to define timing arcs and constraints per spec and deliver to software team.
• Perform quality checks on timing models to confirm all timing arcs meet software requirements.
• Address issues such as missing timing arcs and missing clock information.
• Generate timing reference models based on IP requirements
• Compare timing models: Current proprietary format vs. Liberty format (.lib).
• Handle custom design simulations, use SPICE simulations and additional data to construct proprietary Timing models.
• Generate full chip timing model to bridge between IP timing models, using SPICE simulations or STA reports.
• FPGA power model know-how and knowledge will be added advantage.
• Experience with PrimeTime/Liberate will be added advantage.

Additional Job Description

• 10 yrs experience of hardware integration design
• FPGA timing model know-how and knowledge will be added advantage.
• Successfully went through whole development from start to Tape Out of at least 2 products.
• Proficient in schematic generation using Cadence Virtuoso tool and spice simulation of it.
• Working knowledge of System Verilog, synthesis, and static timing analysis
• Specialist in floor-planning, power estimate, timing and back-end methodologies
• Experience with Linux scripting and Python
• Experience and knowledge of PnR is a plus
• Strong written and oral communication skills
• The ability to stay up-to-date with the latest advancements in technology & design
• Ability to leverage AI tools to accelerate content creation, use AI to analyze large datasets and identify patterns.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

Malaysia

Lattice continually strives to provide a comprehensive compensation and benefits program to attract, retain, motivate, reward and celebrate the highest caliber employees in the industry.

Lattice is an international, service-driven developer of innovative low cost, low power programmable design solutions.

Our global workforce, some 1,000 strong, shares a total commitment to customer success and an unbending will to win.

For more information about how our FPGA, CPLD and programmable power management devices help our customers unlock their innovation, visit www.latticesemi.com.

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At Lattice, we value the diversity of individuals, ideas, perspectives, insights and values, and what they bring to the workplace.