Senior Staff FPGA/SoC Design Engineer—High-Speed Interfaces

Lattice Semiconductor; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

Lattice Semiconductor in Malaysia is seeking a Senior Staff Engineer to lead development, integration, and productization of high-performance interface solutions for next-generation FPGA products. You will own subsystems across PCIe, USB, MIPI, SerDes, and related PHY technologies, collaborating with hardware, software, and design teams.

The role demands a deep RTL background, strong architectural judgment, and the ability to drive cross-functional delivery from pre-silicon to silicon bring-up,

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 15+ years of experience in ASIC, SoC, or FPGA design and product-development.
• Strong RTL design and subsystem integration experience, including clock/reset architecture, configuration interfaces, timing, and CDC/RDC considerations.
• Deep expertise in at least one high-speed interface area such as PCIe, USB, MIPI, SerDes, or related PHY/controller technology.
• Demonstrated ability to understand an interface as a complete subsystem and drive dependencies beyond the RTL block.
• Experience applying AI-assisted tools and workflows to accelerate engineering productivity, technical investigation, data analysis, and documentation.
• Experience working with DFT and DFD methodologies, including scan, ATPG, debug observability, silicon bring-up, or production-test considerations.
• Experience leading complex cross-functional debug and driving issues from initial investigation through verified closure.
• Experience with pre-silicon verification, silicon bring-up, laboratory debug, interoperability, or customer issue resolution.
• Strong technical communication, stakeholder alignment, and independent decision-making skills.

Responsibilities

• Lead architecture and micro-architecture, RTL development, integration, verification, and productization of PCIe, USB, MIPI, SerDes, and related interface subsystems.
• Own subsystem requirements and dependencies across digital logic, PHY/PMA, soft IP, firmware, FPGA software tools, package, platform, and validation.
• Drive structured root-cause analysis for complex pre-silicon, post-silicon, software-interaction, interoperability, and customer-reported issues.
• Work with software and firmware teams to define configuration, feature enablement, diagnostic, and user-flow requirements.
• Drive technical engagement with third-party IP suppliers and technology partners for digital, PHY, and mixed-signal IP. Define requirements, evaluate deliverables, resolve integration and verification issues, and drive technical closure through product development and silicon bring-up.
• Identify technical risks and dependencies, support milestone and release-readiness reviews, and communicate clear recommendations to stakeholders.
• Mentor engineers and improve design, debug, review, and release methodologies across the team.

Skills

RTL design

Subsystem integration

PCIe/USB/MIPI/SerDes

DFT/DFD methodologies

silicon bring-up

AI-assisted tools

technical communication

cross-functional leadership

verification

Education

Bachelor’s or Master’s degree in Electrical/Electronics/Computer Engineering

Tools

DFT tools

EDA tools

Job description

Lattice Semiconductor in Malaysia is seeking a Senior Staff Engineer to lead development, integration, and productization of high-performance interface solutions for next-generation FPGA products. You will own subsystems across PCIe, USB, MIPI, SerDes, and related PHY technologies, collaborating with hardware, software, and design teams.

The role demands a deep RTL background, strong architectural judgment, and the ability to drive cross-functional delivery from pre-silicon to silicon bring-up,