Staff IP Design Engineer — FPGA Connectivity

Lattice Semiconductor; George Town; On-site; MYR 120,000 - 180,000; Full time

Job summary

Lattice Semiconductor is seeking a Staff IP Design engineer in Malaysia to lead connectivity IP portfolios for FPGA projects. You will work closely with architects to translate specifications into high-speed RTL designs that maximize performance, power efficiency and logic utilization.

The role requires hands-on FPGA RTL design, verification, and timing closure, with strong programming skills in C/C++, Python, or scripting. Collaboration with a multi-disciplinary team is essential.

Qualifications

• Experience in high speed SERDES and video protocols (DisplayPort, HDMI, MIPI, SDI) or peripherals (SPI, I2C or I3C).
• Hands-on FPGA RTL design, logic verification, debug and timing closure is preferred.
• Programming skills (C/C++, Perl, TCL or Python).
• Experience in hardware validation or hardware interoperability test is a plus.
• Experience in soft IP packaging, example design and testbench development will be an added advantage.

Responsibilities

• Translate specifications into high-speed RTL design for connectivity IP portfolios in Lattice FPGA.
• Collaborate with architects to optimize performance, power and logic utilization.

Skills

FPGA RTL design

Logic verification

Debug & timing closure

C/C++/Python scripting

Video protocols

Education

BS/MS/PhD in Electronics or Computer Engineering

Job description

Lattice Semiconductor is seeking a Staff IP Design engineer in Malaysia to lead connectivity IP portfolios for FPGA projects. You will work closely with architects to translate specifications into high-speed RTL designs that maximize performance, power efficiency and logic utilization.

The role requires hands-on FPGA RTL design, verification, and timing closure, with strong programming skills in C/C++, Python, or scripting. Collaboration with a multi-disciplinary team is essential.