Senior FPGA DSP IP Design Engineer

LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD.; Penang; On-site; MYR 150,000 - 210,000; Full time

Job summary

Lattice Semiconductor Malaysia Sdn. Bhd. seeks an experienced FPGA IP engineer to design DSP-centric foundation IP blocks and RTL for DSP slices. You will work with cross-functional teams on release cycles, analysis, development, testing and validation to ensure high product quality.

The role requires a strong background in RTL languages, DSP theory and FPGA architecture, with collaboration across software and tools teams to integrate IP into FPGA fabric.

Qualifications

• Bachelor's or Master's degree in Electronics/Electrical Engineering, Computer Engineering, or a related discipline
• 8+ years of experience in IP design or ASIC/FPGA engineering
• Strong proficiency in RTL design using Verilog, VHDL, or SystemVerilog
• Working experience in DSP theory and algorithms: filtering, FFT, fixed-point arithmetic, sample-rate conversion

Responsibilities

• Design and implement DSP-centric foundation IP blocks for FPGA fabric
• Develop RTL for DSP hard macros and programmable DSP slices
• Perform functional simulation and timing analysis to ensure targets are met
• Engage with software and tools teams to model DSP IP in simulation libraries and flows

Skills

RTL design

Verilog

VHDL

SystemVerilog

DSP theory

FPGA/IP engineering

research and development

Education

Bachelor's degree in Electronics/Electrical Engineering or Computer Engineering

Master's degree (preferred)

Tools

Synopsys Design Compiler

PrimeTime

Radiant

Quartus

Job description

Lattice Semiconductor Malaysia Sdn. Bhd. seeks an experienced FPGA IP engineer to design DSP-centric foundation IP blocks and RTL for DSP slices. You will work with cross-functional teams on release cycles, analysis, development, testing and validation to ensure high product quality.

The role requires a strong background in RTL languages, DSP theory and FPGA architecture, with collaboration across software and tools teams to integrate IP into FPGA fabric.