Senior FPGA Timing Model Engineer - Silicon Integration

LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD.; Penang; On-site; MYR 180,000 - 300,000; Full time

Job summary

LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD. is seeking a Silicon Integration Design Engineer focused on timing model development for FPGA projects.

You will collaborate with IP designers to align timing models with tool specs and generate reference models using SPICE or STA reports. The role requires hands-on experience with timing arcs, Liberty formats, and scripting in Linux/Python for validation and automation.

Qualifications

• Experience with timing models and FPGA timing analyses.
• Proficiency in SystemVerilog, synthesis, and static timing analysis.
• Scripting in Linux and Python for automation.
• Familiarity with CAD/EDA tools for timing verification.
• Knowledge of SPICE simulations and timing reference models.

Responsibilities

• Collaborate with IP designers and modelling team to ensure timing model requirements align with FPGA tool specifications.
• Define timing arcs and constraints per spec and deliver to software team.
• Perform quality checks on timing models to confirm all timing arcs meet software requirements.
• Address issues such as missing timing arcs and missing clock information.
• Generate timing reference models based on IP requirements.
• Compare timing models: proprietary format vs. Liberty format (.lib).
• Bridge IP timing models using SPICE simulations or STA reports to full chip timing model.
• Provide FPGA power model know-how; PrimeTime/Liberate knowledge is an advantage.

Skills

Timing model

FPGA timing

SystemVerilog

Linux scripting

Python

Tools

Cadence Virtuoso

PrimeTime

Liberate

SPICE simulations

Liberty format

Job description

LATTICE SEMICONDUCTOR MALAYSIA SDN. BHD. is seeking a Silicon Integration Design Engineer focused on timing model development for FPGA projects.

You will collaborate with IP designers to align timing models with tool specs and generate reference models using SPICE or STA reports. The role requires hands-on experience with timing arcs, Liberty formats, and scripting in Linux/Python for validation and automation.