Senior FPGA Timing & Silicon Integration Engineer

Lattice Semiconductor; Penang; On-site; MYR 90,000 - 130,000; Full time

Job summary

Lattice Semiconductor in Penang, Malaysia, is seeking an experienced FPGA timing model engineer to join our hardware integration team. You will collaborate with IP designers to align timing models with FPGA tool specifications and deliver robust timing references based on SPICE/STA data.

The ideal candidate has 10+ years in hardware integration, strong Cadence Virtuoso experience, and proficiency in SystemVerilog, synthesis, and timing analysis, with scripting skills in Linux and Python to

Qualifications

• 10+ years of hardware integration design and FPGA timing model know-how.
• Expertise in timing model development and verification against IP requirements.
• Proficient in Cadence Virtuoso schematic generation and SPICE simulations.
• Strong knowledge of SystemVerilog, synthesis, and static timing analysis.
• Experience with floor-planning and power estimation in back-end flows.

Responsibilities

• Collaborate with IP designers to ensure timing models meet FPGA tool specs.
• Define timing arcs and constraints per IP specifications for software teams.
• Perform quality checks on timing models and fix missing arcs or clocks.
• Generate full-chip timing models bridging IP models and STA reports.
• Apply Linux scripting and Python to automate timing data analysis.

Skills

Timing model development

Cadence Virtuoso

SystemVerilog

Synthesis

Static timing analysis

Floorplanning

Power estimation

Linux scripting

Python

Tools

Cadence Virtuoso

SPICE

PrimeTime

Liberate

Job description

Lattice Semiconductor in Penang, Malaysia, is seeking an experienced FPGA timing model engineer to join our hardware integration team. You will collaborate with IP designers to align timing models with FPGA tool specifications and deliver robust timing references based on SPICE/STA data.

The ideal candidate has 10+ years in hardware integration, strong Cadence Virtuoso experience, and proficiency in SystemVerilog, synthesis, and timing analysis, with scripting skills in Linux and Python to