Senior Integration Design Engineer - FPGA/Verilog & Tapeout

Lattice Malaysia; Malaysia; On-site; MYR 180,000 - 320,000; Full time

Job summary

Lattice Malaysia is seeking an experienced engineer to contribute to advanced FPGA/CPLD design and integration. The role emphasizes Verilog and SystemVerilog expertise and a strong RTL coding/verification background.

You will work on custom and digital design flows, timing analysis, synthesis, DFT/ATPG, and IP/full-chip verification, collaborating across teams to deliver reliable silicon products and performance.

Qualifications

• BS or MS in Electronics/Computer/Electrical Engineering.
• At least 12 years of proven experience in Custom and Digital Design.
• Expertise in Verilog and SystemVerilog is a must.

Skills

Verilog

SystemVerilog

FPGA design

CPLD design

RTL coding

Synthesis

DFT flow

ATPG generation

IP verification

Project leadership

Fullchip verification

Education

BS or MS in Electronics/Computer/Electrical Engineering

Tools

Cadence Virtuoso

Xcelium

Genus

Innovus

Tempus

Job description

Lattice Malaysia is seeking an experienced engineer to contribute to advanced FPGA/CPLD design and integration. The role emphasizes Verilog and SystemVerilog expertise and a strong RTL coding/verification background.

You will work on custom and digital design flows, timing analysis, synthesis, DFT/ATPG, and IP/full-chip verification, collaborating across teams to deliver reliable silicon products and performance.