Senior FPGA RTL Design Engineer, Embedded Hardware

UST; Seberang Perai; Sur place; MYR 120 000 - 180 000; Plein temps

Résumé du poste

UST is seeking an experienced Senior FPGA/RTL Design Engineer to design, verify, and optimize digital hardware for high-performance embedded systems. The role emphasizes RTL design using VHDL and Verilog, and hands-on work with FPGA devices and tools to deliver robust architectures.

You will collaborate with software, firmware, and test teams, develop testbenches, perform timing analysis, simulate with ModelSim/QuestaSim, and mentor junior engineers in RTL methodologies.

Qualifications

• Bachelor’s or Master’s Degree in Electrical Engineering or related field.

Responsabilités

• Design, develop, verify, and optimize RTL modules using VHDL and Verilog
• Perform timing analysis, synthesis optimizations, and resource utilization improvements
• Integrate, simulate, test, and debug FPGA designs in both pre-silicon and lab environments
• Create and execute testbenches and verification plans for module- and system-level functionality

Connaissances

RTL design

FPGA design

VHDL

Verilog

C

Java

debugging

timing analysis

teamwork

Formation

Bachelor's or Master’s Degree in Electrical Engineering or related field

Outils

ModelSim/QuestaSim

Quartus Prime

Cyclone FPGA

Arria FPGA

Description du poste

UST is seeking an experienced Senior FPGA/RTL Design Engineer to design, verify, and optimize digital hardware for high-performance embedded systems. The role emphasizes RTL design using VHDL and Verilog, and hands-on work with FPGA devices and tools to deliver robust architectures.

You will collaborate with software, firmware, and test teams, develop testbenches, perform timing analysis, simulate with ModelSim/QuestaSim, and mentor junior engineers in RTL methodologies.