RTL FPGA Validation

UST Malaysia; Penang; On-site; MYR 90,000 - 150,000; Full time

Job summary

UST Malaysia is seeking an experienced FPGA/RTL Design Engineer to design, develop, integrate, and verify FPGA-based digital logic for high‑performance networking systems.

You will build RTL modules in Verilog/SystemVerilog for FPGA‑based Ethernet datapaths, optimize timing, and debug on hardware, working with system, hardware, verification, and firmware teams.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics/Computer Engineering or related field.
• 4+ years of FPGA/RTL design experience.
• Strong hands-on expertise in Verilog and/or SystemVerilog RTL design.
• Strong experience designing RTL for high-speed Ethernet applications is essential.
• Good understanding of Ethernet architecture, high-speed packet/data processing, and networking interfaces.
• Strong understanding of digital design concepts including CDC, pipelining, FIFOs, state machines, synchronization, latency, and throughput optimization.
• Experience with FPGA design flows, synthesis, place-and-route, timing constraints, and timing closure.
• Experience with FPGA platforms/tools such as AMD/Xilinx or Intel FPGA is preferred.

Responsibilities

• Design and develop complex RTL modules using Verilog/SystemVerilog for FPGA-based applications.
• Develop and optimize RTL designs for high-speed Ethernet datapaths and interfaces.
• Work on Ethernet-related functions such as MAC/PCS, packet processing, framing, buffering, flow control, and high-speed data paths.
• Perform RTL simulation, debugging, integration, and design verification.
• Perform timing analysis and timing closure, with focus on high-frequency and high-throughput designs.
• Integrate FPGA IP blocks and high-speed interfaces into the overall design.
• Debug FPGA issues in simulation and on hardware using appropriate FPGA debug tools.
• Collaborate with system, hardware, verification, and firmware/software teams throughout the development lifecycle.
• Support design documentation, reviews, bring-up, validation, and technical issue resolution.

Skills

Verilog/SystemVerilog

RTL design

High-speed Ethernet

CDC / clock domain crossing

Pipelining

FIFOs

MAC/PCS interfaces

FPGA toolchains

Education

Bachelor's in Electrical/ Electronics/ Computer Engineering

Master's in Electrical/ Electronics/ Computer Engineering

Tools

AMD/Xilinx FPGA

Intel FPGA

Job description

We are looking for an experienced FPGA/RTL Design Engineer with strong hands‑on experience in RTL design and implementation for high‑speed Ethernet applications. The candidate will be responsible for designing, developing, integrating, and verifying FPGA‑based digital logic for high‑performance networking systems.

Key Responsibilities

• Design and develop complex RTL modules using Verilog/SystemVerilog for FPGA‑based applications.
• Develop and optimize RTL designs for high‑speed Ethernet datapaths and interfaces.
• Work on Ethernet‑related functions such as MAC/PCS, packet processing, framing, buffering, flow control, and high‑speed data paths.
• Perform RTL simulation, debugging, integration, and design verification.
• Perform timing analysis and timing closure, with focus on high‑frequency and high‑throughput designs.
• Integrate FPGA IP blocks and high‑speed interfaces into the overall design.
• Debug FPGA issues in simulation and on hardware using appropriate FPGA debug tools.
• Collaborate with system, hardware, verification, and firmware/software teams throughout the development lifecycle.
• Support design documentation, reviews, bring‑up, validation, and technical issue resolution.

Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
• 4+ years of relevant FPGA/RTL design experience.
• Strong hands‑on expertise in Verilog and/or SystemVerilog RTL design.
• Strong experience designing RTL for high‑speed Ethernet applications is essential.
• Good understanding of Ethernet architecture, high‑speed packet/data processing, and networking interfaces.
• Strong understanding of digital design concepts including clock domain crossing (CDC), pipelining, FIFOs, state machines, synchronization, latency, and throughput optimization.
• Experience with FPGA design flows, synthesis, place-and-route, timing constraints, and timing closure.
• Experience with FPGA platforms/tools such as AMD/Xilinx or Intel FPGA is preferred.
• Strong RTL debugging and problem‑solving skills.