FPGA Design Engineer – Verilog/VHDL, PCIe

UST Malaysia; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

UST Malaysia in Penang is seeking a skilled FPGA engineer to design and implement HDL/IP solutions using Verilog, SystemVerilog and VHDL across diverse FPGA platforms. You will collaborate with international teams, leverage industry tools like Xilinx Vivado and ModelSim, and contribute to high-speed interfaces such as PCIe, Ethernet, USB and memory interfaces.

This role requires a Bachelor's degree in Electrical/Electronic Engineering and 3-5 years of experience, with willingness to work on-site

Qualifications

• Bachelor degree in Electrical/Electronic engineering or equivalent.
• Minimum 3-5 years of direct working experiences in FPGA HDL/IP design.
• Fluent in both written and spoken English, ability to work in an international team.
• Good team work attitude, collaboration and communication skills.
• Willing to work in Bayan Lepas, Penang Malaysia.

Skills

HDL languages Verilog/SystemVerilog/VH

FPGA tools Xilinx Vivado/Vitis Quartus

Simulation tools ModelSim/QuestaSim

High-speed interfaces PCIe Ethernet/US

Low-speed interfaces SPI I2C UART

Education

Bachelor degree in Electrical/Electronic engineering

Job description

UST Malaysia in Penang is seeking a skilled FPGA engineer to design and implement HDL/IP solutions using Verilog, SystemVerilog and VHDL across diverse FPGA platforms. You will collaborate with international teams, leverage industry tools like Xilinx Vivado and ModelSim, and contribute to high-speed interfaces such as PCIe, Ethernet, USB and memory interfaces.

This role requires a Bachelor's degree in Electrical/Electronic Engineering and 3-5 years of experience, with willingness to work on-site