Senior DV Manager - SoC Verification & Tape-Out Lead

Silicon One; Bayan Lepas; On-site; MYR 350,000 - 600,000; Full time

Job summary

Silicon One is seeking an exceptional DV Technical Manager to lead our pre-silicon functional verification for PCIe, Ethernet, ARM SoC architectures and DDR/LPDDR memory subsystems. You will build a high-performing team, define verification roadmaps, and drive execution across ASIC/SoC projects to tape-out readiness.

In this leadership role you will manage a verification engineering group, establish methodologies, master vPlans, and collaborate with system architects, RTL leads and post-silicon

Qualifications

• Expert-level SystemVerilog fluency; OOP concepts, constraints, functional coverage.
• Extensive experience verifying ARM-based SoCs and high-speed interconnects (PCIe, Ethernet, DDR/LPDDR).
• Proficiency with industry-standard simulators and advanced debug tools.

Responsibilities

• Lead and mentor the verification engineering team; drive career growth and best practices.
• Define verification strategies, vPlans, and execution roadmaps for ARM interconnects, PCIe, Ethernet, and memory controllers.
• Oversee testbench architecture using SystemVerilog/UVM for multiple chip projects.
• Drive functional/code coverage closure, assertions, and regression towards tape-out milestones.
• Allocate resources and plan projects to mitigate risks early.

Skills

SystemVerilog

ARM SoC verification

PCIe

Ethernet

DDR/LPDDR memory

Python

Perl

Bash

Make

CI pipelines

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Verdi

Job description

Silicon One is seeking an exceptional DV Technical Manager to lead our pre-silicon functional verification for PCIe, Ethernet, ARM SoC architectures and DDR/LPDDR memory subsystems. You will build a high-performing team, define verification roadmaps, and drive execution across ASIC/SoC projects to tape-out readiness.

In this leadership role you will manage a verification engineering group, establish methodologies, master vPlans, and collaborate with system architects, RTL leads and post-silicon