Design Verification Technical Manager

Silicon One; Bayan Lepas; On-site; MYR 350,000 - 600,000; Full time

Job summary

Silicon One is seeking an exceptional DV Technical Manager to lead our pre-silicon functional verification for PCIe, Ethernet, ARM SoC architectures and DDR/LPDDR memory subsystems. You will build a high-performing team, define verification roadmaps, and drive execution across ASIC/SoC projects to tape-out readiness.

In this leadership role you will manage a verification engineering group, establish methodologies, master vPlans, and collaborate with system architects, RTL leads and post-silicon

Qualifications

• Expert-level SystemVerilog fluency; OOP concepts, constraints, functional coverage.
• Extensive experience verifying ARM-based SoCs and high-speed interconnects (PCIe, Ethernet, DDR/LPDDR).
• Proficiency with industry-standard simulators and advanced debug tools.

Responsibilities

• Lead and mentor the verification engineering team; drive career growth and best practices.
• Define verification strategies, vPlans, and execution roadmaps for ARM interconnects, PCIe, Ethernet, and memory controllers.
• Oversee testbench architecture using SystemVerilog/UVM for multiple chip projects.
• Drive functional/code coverage closure, assertions, and regression towards tape-out milestones.
• Allocate resources and plan projects to mitigate risks early.

Skills

SystemVerilog

ARM SoC verification

PCIe

Ethernet

DDR/LPDDR memory

Python

Perl

Bash

Make

CI pipelines

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Verdi

Job description

Silicon One is seeking an exceptional DV Technical Manager with deep domain expertise in PCIe, Ethernet, ARM SoC architectures, and DDR/LPDDR memory subsystems to guide and drive our pre-silicon functional verification strategy. In this leadership role, you will lead and manage the verification engineering team, establishing methodologies, defining architectural verification roadmaps, managing team resources, and driving execution across complex ASIC/SoC projects. Your mission is to build and empower a high-performing engineering team to exhaustively verify complex designs, close coverage targets, and deliver zero-bug tape-outs.

Key Responsibilities

• Team Management & Leadership: Manage, recruit, and mentor the design verification engineering team, guiding career growth, performance reviews, and fostering best practices in verification methodologies and regression flows.
• Verification Strategy & Planning: Partner with system architects and RTL design leads to define overall verification strategies, master Verification Plans (vPlans), and execution roadmaps for ARM SoC interconnects, PCIe links, Ethernet MAC/PHY, and DDR/LPDDR memory controllers.
• Testbench Architecture Oversight: Architect and oversee the development of reusable, scalable SystemVerilog/UVM testbenches and scalable verification environments across multiple chip projects.
• Execution & Closure Management: Track and drive progress on functional/code coverage closure, assertion-based verification, and regression completion toward strict tape-out milestones.
• Resource Allocation & Project Planning: Collaborate with engineering management to plan project schedules, allocate verification resources, and mitigate technical risks early in the execution cycle.
• Advanced Debug & Escalation Lead: Serve as the lead technical point for resolving critical system-level debug issues and complex corner-case RTL failures using advanced waveform and debug tools.
• Cross-Functional Collaboration: Act as the main technical liaison between verification, design, emulation, and post-silicon validation teams to ensure aligned tape-out readiness goals.

Required Qualifications

• Experience & Leadership: 15+ years of experience in ASIC/SoC Functional Design Verification, including demonstrated experience managing or leading verification teams.
• Languages: Expert-level fluency in SystemVerilog (OOP concepts, constraints, functional coverage).
• Protocol & SoC Expertise: Extensive experience verifying complex ARM-based SoCs and high-speed protocols/interfaces including PCIe, Ethernet, and DDR/LPDDR memory controllers.
• EDA Tools: Extensive experience with industry-standard logic simulators (Synopsys VCS, Cadence Xcelium, or Siemens Questa) and debuggers (Verdi).
• Automation: Strong scripting skills in Python, Perl, Bash, or Make to build and maintain regression environments, CI pipelines, and parsing tools.

Preferred Skills

• Experience writing or integrating C/C++ Golden Reference Models via SystemVerilog DPI-C.
• Deep architectural and verification experience with ARM AMBA interconnects (AXI, AHB, CHI, ACE) and VIP integrations for PCIe, Ethernet, and DDR/LPDDR standards.

Familiarity with Formal Verification tools and methodologies (e.g., JasperGold).

Why Silicon One?

• Full Lifecycle Exposure: Drive designs from initial specification through to successful tape-out.
• Competitive Rewards: We offer a highly attractive compensation package for top-tier lead talent.