Senior ASIC DV Lead — UVM, Formal & Emulation

SkyeChip Berhad; Penang; On-site; MYR 180,000 - 320,000; Full time

Job summary

SkyeChip Berhad is seeking an experienced ASIC DV Manager to lead and grow the verification engineering team, owning full verification methodology and execution quality across multiple concurrent customer engagements.

This hands‑on technical leadership role involves reviewing UVM architectures, defining coverage closure strategies, writing constraint blocks, and presenting risk and schedule status to customers with confidence.

Qualifications

• 10+ years of hands‑on ASIC functional verification experience, with 3+ years in a lead or management capacity.
• Deep expertise in SystemVerilog and UVM; able to architect and critically review complex agent, scoreboard, and coverage collector implementations.
• Strong command of coverage‑driven and constraint‑random verification methodology.
• Proficiency with industry‑standard simulation tools: Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Hands‑on experience with formal property verification: JasperGold, Questa Formal, or equivalent.
• Experience with CDC/RDC analysis flows: SpyGlass, Questa CDC, or equivalent.
• Python or Perl scripting for regression automation, coverage analysis, and flow integration.

Responsibilities

• Build, manage, and mentor a team of DV engineers spanning RTL simulation, formal verification, and emulation.
• Define team structure, hiring roadmap, and individual competency development plans.
• Conduct rigorous technical reviews and drive engineering excellence standards across the group.
• Partner with Physical Design, RTL Design, and Project Management leads on integrated project execution.
• Define regression infrastructure strategy including farm utilization, CI integration, and nightly regression hygiene.
• Interface directly with customers on DV scope definition, milestone reviews, and bug triage.

Job description

SkyeChip Berhad is seeking an experienced ASIC DV Manager to lead and grow the verification engineering team, owning full verification methodology and execution quality across multiple concurrent customer engagements.

This hands‑on technical leadership role involves reviewing UVM architectures, defining coverage closure strategies, writing constraint blocks, and presenting risk and schedule status to customers with confidence.