Senior Engineer I - ASIC Verification

Microchip Technology Inc.; Penang; On-site; MYR 180,000 - 240,000; Full time

Job summary

Microchip Technology Inc. is seeking a seasoned verification engineer to verify DDR4/DDR5 memory controllers and AXI interfaces, ensuring protocol compliance and data integrity. You will build UVM environments, write constrained-random tests, and collaborate with design and firmware teams.

The role requires 10+ years in SoC/IP-level verification, strong SystemVerilog/UVM skills, and experience with major simulators. Penang-based position with potential travel.

Qualifications

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.

Responsibilities

• Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controllers and PHY IP.

Skills

DDR protocol

SystemVerilog

UVM

AXI protocol

Python scripting

AI/LLM-assisted workflows

GLS familiarity

Debugging

Education

Bachelor/Master in Electronics, Electrical or Computer Engineering

Tools

Synopsys VCS

Cadence Xcelium

Mentor Questa

Job description

Are you looking for a unique opportunity to be a part of something great? Want to join a 17,000-member team that works on the technology that powers the world around us? Looking for an atmosphere of trust, empowerment, respect, diversity, and communication? How about an opportunity to own a piece of a multi-billion dollar (with a B!) global organization? We offer all that and more at Microchip Technology Inc.

People come to work at Microchip because we help design the technology that runs the world. They stay because our culture supports their growth and stability. They are challenged and driven by an incredible array of products and solutions with unlimited career potential. Microchip’s nationally-recognized Leadership Passage Programs support career growth where we proudly enroll over a thousand people annually. We take pride in our commitment to employee development, values-based decision making, and strong sense of community, driven by our Vision, Mission, and 11 Guiding Values; we affectionately refer to it as the Aggregate System and it’s won us countless awards for diversity and workplace excellence.

Our company is built by dedicated team players who love to challenge the status quo; we did not achieve record revenue and over 30 years of quarterly profitability without a great team dedicated to empowering innovation. People like you.

Visit our careers page to see what exciting opportunities and company perks await!

Job Description

Role Overview

You will be responsible for verifying DDR4/5 memory controllers and AXI input interfaces for IP-level designs, ensuring full protocol compliance, error handling, data integrity and performance computation for high-speed DDR interfaces.

Key Responsibilities

• Develop and maintain SystemVerilog UVM-based verification environments for DDR4/DDR5 memory controller and PHY IP.
• Define verification plans, design testbenches, and create directed and constrained-random testcases.
• Write and debug testcases and sequences for DDR protocol features (read/write operations, refresh, training, power-down modes).
• Validate ECC, parity, and command/address/data integrity mechanisms.
• Develop and debug scoreboards, assertions (SVA), and checkers for data integrity and protocol correctness.
• Integrate AXI, APB VIPs with DDR subsystem.
• Perform coverage analysis (code, functional, assertion) to ensure verification completeness.
• Debug RTL and simulation failures using waveform analysis (SimVision, Verdi).
• Work with design teams to debug RTL and root-cause functional/timing issues in RTL and GLS.
• Collaborate with post-silicon and firmware teams for memory bring-up and validation.
• Mentor verification engineers and drive best practices

Technical Skills

• Strong knowledge of DDR protocol (JEDEC specifications).
• Experience with SystemVerilog, UVM, and verification methodology.
• Hands-on with simulation tools like Synopsys VCS, Cadence Xcelium, or Mentor Questa.
• Good understanding of memory controller architecture and timing parameters (setup/hold, tRCD, tRP, etc.).
• Knowledge of AXI protocol and its integration with DDR controller.
• Familiarity with assertions (SVA), scoreboarding, and functional coverage. Familiarity with GLS is a plus.
• Drive debug efficiency improvements by leveraging modern methodologies, script automation (Python), and integrating AI/LLM-assisted workflows to accelerate root-cause analysis and triage.

Soft Skills

• Strong analytical and debugging skills.
• Able to deliver tasks independently.
• Good communication and leadership skills.
• Comfortable collaborating across design, validation, and firmware teams.

Requirements/Qualifications

B.E/B.Tech or M.E/M.Tech in Electronics, Electrical, or Computer Engineering.

10+ years of experience in SoC or IP-level verification (memory subsystems preferred)

Travel Time

0% - 25%