Senior DFT Engineer – SoC Test & Post-Silicon AI

Intel Corporation; Penang; On-site; MYR 120,000 - 210,000; Full time

Job summary

Intel Malaysia in Penang is seeking a seasoned DFT Design Engineer to shape testability, debuggability and reliability of complex SoCs. You will collaborate with cross-functional teams to influence designs from concept to production and implement innovative DFT/DFD methodologies with AI-driven workflows.

This role requires a strong background in RTL with Verilog/VHDL/SystemVerilog, 5+ years in DFT or related semiconductor design, and familiarity with industry standards such as IEEE 1687 and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in DFT, SoC design, or related semiconductor design areas.
• Expertise in RTL design using Verilog, VHDL, or SystemVerilog.

Responsibilities

• Develop and implement advanced DFT methodologies for complex SoC designs to maximize test coverage and efficiency.
• Collaborate with design, verification, and manufacturing teams to define and optimize post silicon strategies and requirements.
• Integrate DFT/DFD features into RTL and ensure verification of design for testability requirements.
• Collaborate with post-silicon teams to debug and validate DFT features.
• Stay current with emerging trends, AI adoption and technologies in DFT/DFD to ensure best practices are incorporated into workflows.

Skills

DFT design

RTL design

SystemVerilog

Verilog

SoC design

Python scripting

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synopsys DFT Compiler

Mentor Tessent

Cadence Modus

IJTAG/JTAG familiarity

Job description

Intel Malaysia in Penang is seeking a seasoned DFT Design Engineer to shape testability, debuggability and reliability of complex SoCs. You will collaborate with cross-functional teams to influence designs from concept to production and implement innovative DFT/DFD methodologies with AI-driven workflows.

This role requires a strong background in RTL with Verilog/VHDL/SystemVerilog, 5+ years in DFT or related semiconductor design, and familiarity with industry standards such as IEEE 1687 and