Lead DFT Engineer - SoC/ASIC Test & Automation

Pride Global; Seberang Perai; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global is seeking an experienced Design-for-Test (DFT) Engineer in Malaysia to develop and implement DFT solutions for high-performance ASICs and SoCs. The role emphasizes high test coverage, optimized cost, and efficient execution while maintaining power, performance, and area targets.

Responsibilities include defining chip-level DFT, integrating scan compression with industry tools, and generating ATPG patterns.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering required.
• 4–15 years hands-on ASIC/SoC DFT experience a must.
• Strong knowledge of Verilog/SystemVerilog/VHDL and digital design.
• Experience with production DFT flows, ATPG, and silicon debug preferred.

Responsibilities

• Define and implement chip-level DFT architecture including scan, MBIST, LBIST, JTAG, and IEEE 1500 wrapper chains.
• Develop test strategies, clock/reset architectures, and DFT specifications for complex SoCs.
• Integrate scan compression using Synopsys DFTMAX, Tessent, and Cadence tools.
• Generate and optimize ATPG patterns for multiple fault models.
• Verify DFT via RTL and gate-level simulations; perform pre- and post-layout validation.
• Support silicon bring-up, ATE debugging, failure analysis, and yield improvement.
• Develop automation scripts in Tcl, Python or Perl to improve DFT flow efficiency.

Skills

Verilog

SystemVerilog

VHDL

Digital design

Synthesis

Tcl scripting

Python scripting

Perl scripting

ATPG/DFT

MBIST/LBIST

JTAG/IEEE 1500

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Synopsys DFTMAX

Cadence Genus

Siemens Tessent

Cadence Modus

Job description

Pride Global is seeking an experienced Design-for-Test (DFT) Engineer in Malaysia to develop and implement DFT solutions for high-performance ASICs and SoCs. The role emphasizes high test coverage, optimized cost, and efficient execution while maintaining power, performance, and area targets.

Responsibilities include defining chip-level DFT, integrating scan compression with industry tools, and generating ATPG patterns.