Senior AMS Verification Engineer: Master Mixed-Signal

UST; Penang; On-site; MYR 150,000 - 300,000; Full time

Job summary

UST is seeking an experienced AMS verification engineer in Penang to define and execute verification strategies for complex mixed-signal ICs. You will analyze specifications, derive comprehensive test cases, and develop robust verification environments with automated regression flows to ensure product quality.

The role requires 7+ years in analog/mixed-signal verification, strong knowledge of SystemVerilog, UVM, and hands-on experience with Cadence tools.

Qualifications

• Requires a degree in Electrical/Electronics/Microelectronics/Automation or related field.
• 7+ years in analog/mixed-signal IC design, verification, modeling, or simulation.
• Strong AMS verification and simulation experience.

Responsibilities

• Define and execute AMS/system verification strategies and plans for complex mixed-signal ICs.
• Analyze specs and derive verification scenarios and test cases.
• Develop and maintain verification environments, testbenches, and regression flows.

Skills

AMS verification

SystemVerilog

Verilog RTL

UVM

Regression flows

Root-cause analysis

Analog/mixed-signal behavior

Debugging complex simulations

Education

Bachelors/Masters in Electrical/Electronics/Microelectronics/Automation

Tools

Cadence Spectre

Cadence AMS Designer

Cadence Xcelium

Siemens Symphony

Job description

UST is seeking an experienced AMS verification engineer in Penang to define and execute verification strategies for complex mixed-signal ICs. You will analyze specifications, derive comprehensive test cases, and develop robust verification environments with automated regression flows to ensure product quality.

The role requires 7+ years in analog/mixed-signal verification, strong knowledge of SystemVerilog, UVM, and hands-on experience with Cadence tools.