Senior Mixed-Signal AMS Verification Engineer

UST Malaysia; Bayan Lepas; Sur place; MYR 180 000 - 260 000; Plein temps

Résumé du poste

UST Malaysia in Penang is seeking an experienced AMS verification engineer to define and execute verification strategies for complex mixed-signal ICs. You will analyze specifications, develop testbenches, and collaborate with analog and digital teams to ensure robust silicon bring-up and reliable measurements.

The role emphasizes automation, regression flows, and strong problem-solving across multi-site teams, with a focus on achieving high verification coverage and model accuracy.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, Automation, or a related technical discipline.
• 7+ years of relevant experience in analog/mixed-signal IC design, verification, modeling, or simulation.
• Strong experience in Analog Mixed-Signal verification and simulation.
• Experience with industry-standard AMS simulation environments such as Cadence Spectre, Cadence AMS Designer, Cadence Xcelium, Siemens Symphony, or comparable mixed-signal simulation platforms.
• Strong understanding of analog and mixed-signal circuit behavior and system interactions.
• Good knowledge of SystemVerilog.
• Solid understanding of Verilog RTL and digital design concepts.
• Strong analytical and problem-solving skills.

Responsabilités

• Define and execute AMS/System Verification strategies and verification plans for complex mixed-signal ICs.
• Analyze product specifications, system requirements, design specifications, and application requirements to derive comprehensive verification scenarios and test cases.
• Develop and maintain mixed-signal verification environments, testbenches, test cases, checkers, and automated regression flows.
• Verify system functionality using advanced Analog Mixed-Signal simulation tools, including transistor-level, behavioral-level, and mixed-abstraction simulations.
• Work closely with analog and digital design teams to define appropriate verification interfaces, simulation configurations, models, and abstraction levels.
• Verify interaction and synchronization between analog and digital domains, particularly for timing-critical and power-management systems.
• Develop, review, and integrate behavioral models to improve verification performance while maintaining the required model accuracy.
• Perform verification of analog functions such as regulators, references, oscillators, amplifiers, charge pumps, monitoring circuits, protection functions, power sequencing, and control loops.
• Verify digital-to-analog and analog-to-digital interactions, including register-controlled analog functionality, state-machine behavior, fault handling, startup, shutdown, and power-sequencing scenarios.
• Develop reusable verification components and methodologies using SystemVerilog and UVM, where appropriate.
• Plan and execute verification of Design-For-Test (DFT), test modes, fault conditions, diagnostic functions, and safety-related features where applicable.
• Establish and maintain automated simulation and regression environments and analyze failures across large regression suites.
• Perform root-cause analysis of verification failures and work closely with design teams to identify and resolve design, model, testbench, and specification issues.
• Track verification progress, test status, requirements coverage, simulation results, and identified issues throughout the project lifecycle.
• Participate in design reviews, verification reviews, specification reviews, and project milestone assessments.
• Support silicon bring-up, validation, debugging, and correlation between simulation and laboratory measurements when required.
• Contribute to continuous improvement of AMS verification methodologies, simulation performance, automation, behavioral modeling, and verification quality.
• Provide technical guidance and mentoring to verification engineers and contribute to knowledge sharing and best-practice development within the team.
• Work effectively within multi-site and cross-functional development teams.

Connaissances

AMS verification

SystemVerilog

UVM

mixed-signal verification

root-cause analysis

regression automation

debugging

team collaboration

Formation

Bachelor's or Master's degree in Electrical Engineering / Microelectronics

Outils

Cadence Spectre

Cadence AMS Designer

Cadence Xcelium

Siemens Symphony

Equivalent mixed-signal simulators

Description du poste

UST Malaysia in Penang is seeking an experienced AMS verification engineer to define and execute verification strategies for complex mixed-signal ICs. You will analyze specifications, develop testbenches, and collaborate with analog and digital teams to ensure robust silicon bring-up and reliable measurements.

The role emphasizes automation, regression flows, and strong problem-solving across multi-site teams, with a focus on achieving high verification coverage and model accuracy.