Senior AMS Verification Engineer

UST; Penang; On-site; MYR 150,000 - 300,000; Full time

Job summary

UST is seeking an experienced AMS verification engineer in Penang to define and execute verification strategies for complex mixed-signal ICs. You will analyze specifications, derive comprehensive test cases, and develop robust verification environments with automated regression flows to ensure product quality.

The role requires 7+ years in analog/mixed-signal verification, strong knowledge of SystemVerilog, UVM, and hands-on experience with Cadence tools.

Qualifications

• Requires a degree in Electrical/Electronics/Microelectronics/Automation or related field.
• 7+ years in analog/mixed-signal IC design, verification, modeling, or simulation.
• Strong AMS verification and simulation experience.

Responsibilities

• Define and execute AMS/system verification strategies and plans for complex mixed-signal ICs.
• Analyze specs and derive verification scenarios and test cases.
• Develop and maintain verification environments, testbenches, and regression flows.

Skills

AMS verification

SystemVerilog

Verilog RTL

UVM

Regression flows

Root-cause analysis

Analog/mixed-signal behavior

Debugging complex simulations

Education

Bachelors/Masters in Electrical/Electronics/Microelectronics/Automation

Tools

Cadence Spectre

Cadence AMS Designer

Cadence Xcelium

Siemens Symphony

Job description

• Define and execute AMS/System Verification strategies and verification plans for complex mixed-signal ICs.
• Analyze product specifications, system requirements, design specifications, and application requirements to derive comprehensive verification scenarios and test cases.
• Develop and maintain mixed-signal verification environments, testbenches, test cases, checkers, and automated regression flows.
• Verify system functionality using advanced Analog Mixed-Signal simulation tools, including transistor-level, behavioral-level, and mixed-abstraction simulations.
• Work closely with analog and digital design teams to define appropriate verification interfaces, simulation configurations, models, and abstraction levels.
• Verify interaction and synchronization between analog and digital domains, particularly for timing-critical and power-management systems.
• Develop, review, and integrate behavioral models to improve verification performance while maintaining the required model accuracy.
• Perform verification of analog functions such as regulators, references, oscillators, amplifiers, charge pumps, monitoring circuits, protection functions, power sequencing, and control loops.
• Verify digital-to-analog and analog-to-digital interactions, including register-controlled analog functionality, state-machine behavior, fault handling, startup, shutdown, and power-sequencing scenarios.
• Develop reusable verification components and methodologies using SystemVerilog and UVM, where appropriate.
• Plan and execute verification of Design-For-Test (DFT), test modes, fault conditions, diagnostic functions, and safety-related features where applicable.
• Establish and maintain automated simulation and regression environments and analyze failures across large regression suites.
• Perform root-cause analysis of verification failures and work closely with design teams to identify and resolve design, model, testbench, and specification issues.
• Track verification progress, test status, requirements coverage, simulation results, and identified issues throughout the project lifecycle.

Job Requirements

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, Microelectronics, Automation, or a related technical discipline.
• Typically 7+ years of relevant experience in analog/mixed-signal IC design, verification, modeling, or simulation, or equivalent demonstrated expertise.
• Strong experience in Analog Mixed-Signal verification and simulation.
• Expertise with industry-standard AMS simulation environments such as Cadence Spectre, Cadence AMS Designer, Cadence Xcelium, Siemens Symphony, or comparable mixed-signal simulation platforms.
• Strong understanding of analog and mixed-signal circuit behavior and system interactions.
• Good knowledge of common analog circuit blocks, including LDOs and voltage regulators, DC/DC converters, bandgap and voltage/current references, oscillators and clock circuits, operational amplifiers and comparators, charge pumps, monitoring and protection circuits, and power sequencing and reset circuits.
• Experience developing verification plans, test cases, simulation environments, and automated regression flows.
• Experience debugging complex mixed-signal simulation failures involving interactions between analog models, transistor-level circuits, RTL, and verification environments.
• Good knowledge of SystemVerilog.
• Solid understanding of Verilog RTL and digital design concepts.
• Strong analytical and problem-solving skills. Ability to work independently, take technical own