Senior SoC Physical Design Manager | High Salary | Mandarin speaker

ThunderSoft; Penang; On-site; MYR 120,000 - 180,000; Full time

Benefits offered by this job

High salary package

Job summary

ThunderSoft in Penang, Malaysia, is seeking experienced Physical Design Engineers for a high-performance SoC project. You’ll work on floorplanning, placement, CTS, routing, and timing closure as part of a global engineering team.

If you enjoy solving timing, power, and congestion challenges and have at least 5 years of PD hands-on experience, you’ll fit well. Chinese and English communication skills are highly valued in this cross-regional collaboration.

Qualifications

• 5+ years of hands-on Physical Design experience.
• Solid understanding of: STA, timing closure, CTS, floorplanning, low-power implementation.
• Experience in full-chip or subsystem-level implementation.
• TCL / Perl / Python.
• Multiple tapeout experience is highly preferred.
• Fluent Chinese & English communication skills.

Responsibilities

• Participate in floorplanning, placement, CTS, routing, STA and timing closure.
• Lead advanced SoC physical design optimizations (PPA, congestion, power, IR drop, clock & timing analysis).
• Set up SDC constraints and perform timing debugging.
• Provide physical verification and tapeout support.
• Collaborate with architecture, RTL, DFT and verification teams across global sites.
• Support advanced-node implementation and low-power design methodologies.

Skills

Physical Design

Timing Closure

Floorplanning

CTS

Power Integrity

Scripting (TCL/Perl/Python)

Tapeout Experience

English/Chinese Communication

Job description

Chinese communication ability is highly preferred due to cross-regional engineering collaboration.

High Salary Package | Leading Semiconductor Project

We are looking for experienced Physical Design Engineers to join a high-performance semiconductor project focused on advanced SoC development.

This role offers the opportunity to work on complex full-chip implementation and advanced-node designs together with global engineering teams.

If you enjoy solving challenging timing, congestion, power, and physical implementation problems — this could be a strong fit for you.

What You’ll Work On

• Floorplanning, Placement, CTS, Routing, STA & Timing Closure
• Advanced SoC physical design optimization: PPA, congestion, power, IR drop, clock & timing analysis
• SDC constraints setup and timing debugging
• Physical verification and tapeout support
• Collaboration with architecture, RTL, DFT and verification teams across global sites
• Advanced-node implementation and low-power design methodologies

What We’re Looking For

• 5+ years of hands-on Physical Design experience
• Solid understanding of: STA, timing closure, CTS, floorplanning, low-power implementation
• Experience in full-chip or subsystem-level implementation
• TCL / Perl / Python
• Multiple tapeout experience is highly preferred
• Fluent Chinese & English communication skills

Why This Opportunity?

• High-paying package with strong technical exposure
• Work on advanced semiconductor / SoC projects
• Exposure to global engineering collaboration
• Strong technical ownership and long-term growth
• Opportunity to work with experienced industry experts