Lead ASIC Design Architect – RTL to Tapeout

Microchip Technology Inc.; Penang; On-site; MYR 240,000 - 360,000; Full time

Job summary

Microchip Technology Inc. in Penang, Malaysia seeks an experienced ASIC Design Lead with 12–16 years in IC design. You will drive architectural and RTL implementation, sign off timing, and mentor the team using Cadence Genus, DesignCompiler, Tempus and PrimeTime.

Familiarity with advanced nodes and System-Verilog is essential. You will collaborate with project managers and CAD teams to optimize flow, power, and test coverage while documenting procedures and ensuring robust outcomes for tapeout

Qualifications

• Bachelor’s/Master’s Degree in Electrical/Electronics Engineering with 12-16 years of ASIC IC design experience.
• Cadence Genus or Synopsys DesignCompiler expertise.
• Cadence Tempus or Synopsys Primetime expertise.
• Exposure to 7nm and below advanced process nodes.
• Familiar with System-Verilog and coding.
• Strong scripting skills in Perl, TCL, Shell or Python.

Responsibilities

• Lead technically in ASIC design implementation from architecture to timing signoff for tapeout.
• Develop and signoff RTL2GDS implementation and flow improvements.
• Understand architectural and micro-architectural intent for design.
• DFT implementation covering scan insertion, compression and related techniques.
• Drive low power design through architectural feedback and optimization.
• Provide technical guidance and mentorship to team members.
• Document design approaches and system procedures per corporate standards.

Skills

ASIC design

Technical leadership

RTL design

Problem solving

Education

Bachelor's/Master's in Electrical/Electronics Engineering

Tools

Cadence Genus

Synopsys DesignCompiler

Cadence Tempus

Synopsys Primetime

Job description

Microchip Technology Inc. in Penang, Malaysia seeks an experienced ASIC Design Lead with 12–16 years in IC design. You will drive architectural and RTL implementation, sign off timing, and mentor the team using Cadence Genus, DesignCompiler, Tempus and PrimeTime.

Familiarity with advanced nodes and System-Verilog is essential. You will collaborate with project managers and CAD teams to optimize flow, power, and test coverage while documenting procedures and ensuring robust outcomes for tapeout