Senior Testchip Design Lead - Automation & Tape-In

Intel Corporation; George Town; Híbrido; MYR 180.000 - 260.000; Jornada completa

Descripción de la vacante

Intel Corporation in Malaysia, Penang, seeks a Senior Engineer to lead end-to-end testchip design and tape-in delivery for advanced process nodes. This hands-on technical leadership role requires deep expertise in design rule validation, test structure design, and layout execution, with strong cross-functional collaboration and program management capabilities.

The role focuses on driving testchip execution end-to-end, applying runset expertise, owning full-flow layout, and delivering Tape-In on

Formación

• Hands-on experience in layout design, test structure development, and flow methodology.
• DRC-clean sign-off on advanced process nodes for corecells and DUTs.
• Strong ability to interpret runset into effective test structure strategies.
• Experience leading and managing cross-site teams with delivery focus.

Responsabilidades

• Drive testchip execution end-to-end across multiple component blocks and tape-in readiness.
• Apply deep design rule and runset expertise to define test structure requirements.
• Own full-flow layout execution from environment setup to DRC-clean sign-off.
• Deliver integration and Tape-In on schedule including Testrow integration.
• Define and deploy automation/AI strategies for repetitive tasks and reporting.
• Lead cross-site collaboration and proactive communication among design, yield, process, and integration teams.
• Mentor and grow the team with clear expectations and technical guidance.

Conocimientos

Python

Tcl

Perl

Automation

Educación

Bachelor's degree in Electrical/Computer Engineering

Master’s degree preferred

Descripción del empleo

Intel Corporation in Malaysia, Penang, seeks a Senior Engineer to lead end-to-end testchip design and tape-in delivery for advanced process nodes. This hands-on technical leadership role requires deep expertise in design rule validation, test structure design, and layout execution, with strong cross-functional collaboration and program management capabilities.

The role focuses on driving testchip execution end-to-end, applying runset expertise, owning full-flow layout, and delivering Tape-In on