Senior ASIC Design Engineer – Synthesis & Timing Expert

Bitdeer Technologies Group; Seberang Perai; On-site; MYR 180,000 - 280,000; Full time

Job summary

Bitdeer Technologies Group seeks a seasoned IC design engineer in Penang to drive synthesis, timing closure, and power optimization for ASIC designs. You will collaborate with DFT and physical design teams to optimize floorplans, P&R, and timing bottlenecks while ensuring formal verification of netlists.

The ideal candidate has 3–7 years in IC design, solid Verilog/SystemVerilog skills, and hands-on experience with leading EDA tools and multi-clock domains.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 3–7 years of IC design experience focusing on synthesis, timing closure, and power optimization.
• Proficiency in Verilog/SystemVerilog, RTL-to-GDSII flow, and EDA tools (Synopsys Design Compiler, Cadence Genus, PrimeTime, Innovus).
• Strong understanding of timing analysis, multi-clock domain handling, and clock tree synthesis.
• Familiarity with on-chip interconnect architectures (AXI, NoC, mesh, torus).
• Experience in low-power design methodologies (UPF, power gating, dynamic voltage scaling).
• Proficiency in scripting (TCL, Python, Perl, Shell) for automation.

Responsibilities

• Synthesis & Logic Optimization for ASIC designs.
• STA, timing closure, and clock tree optimization for high-frequency data pipelines.
• Power & area optimization using low-power techniques; collaborate with DFT engineers.
• Work with Physical Design teams for floorplanning, P&R, and timing bottlenecks.
• Formal verification & equivalence checking using formal tools.

Skills

Verilog/SystemVerilog

RTL-to-GDSII flow

EDA tools

Timing analysis

Multi-clock domains

Clock tree synthesis

Scripting

NoC interconnects

Education

Bachelor’s or Master’s degree in Electrical/Computer Eng

Tools

Synopsys Design Compiler

Cadence Genus

PrimeTime

Innovus

Job description

Bitdeer Technologies Group seeks a seasoned IC design engineer in Penang to drive synthesis, timing closure, and power optimization for ASIC designs. You will collaborate with DFT and physical design teams to optimize floorplans, P&R, and timing bottlenecks while ensuring formal verification of netlists.

The ideal candidate has 3–7 years in IC design, solid Verilog/SystemVerilog skills, and hands-on experience with leading EDA tools and multi-clock domains.