AI-Driven Front-End ASIC/SoC Design Engineer

AMD; George Town; On-site; MYR 180,000 - 280,000; Full time

Job summary

AMD in Penang, Malaysia invites a Senior Front End Integration Silicon Design Engineer to join our ASIC/SoC team. You will drive front-end implementation, RTL-to-netlist flow, and collaborate with PD to deliver high-quality silicon across advanced processes.

Ideal candidates bring 8–10 years in Verilog RTL, front-end EDA toolchains, and proven ability to work across multi-site teams. A degree in Computer or Electrical Engineering is required.

Qualifications

• Solid foundation in ASIC/SoC design and verification.
• Experience with front-end RTL design and verification.
• Hands-on experience developing or applying AI solutions for engineering workflows.

Responsibilities

• Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design.
• Develop ASIC design methodology and flow, interfacing with EDA vendors on technology.
• Ensure timing, lower power, and netlist quality checks with RTL and PD teams.

Skills

Verilog RTL design

ASIC/SoC design

Front-end EDA tools

Unix/Linux scripting

Team collaboration

Education

Bachelor's or Master's in Computer/Electrical & Electronics Engineering

Tools

Design Compiler

PrimeTime

Conformal

VSI/VC-static

Formality

Job description

AMD in Penang, Malaysia invites a Senior Front End Integration Silicon Design Engineer to join our ASIC/SoC team. You will drive front-end implementation, RTL-to-netlist flow, and collaborate with PD to deliver high-quality silicon across advanced processes.

Ideal candidates bring 8–10 years in Verilog RTL, front-end EDA toolchains, and proven ability to work across multi-site teams. A degree in Computer or Electrical Engineering is required.