IC Package Design Engineer (Flip Chip-Substrate)

UST Global; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

Jora Malaysia is seeking a Package Design Engineer with 5–8 years of experience in advanced IC packaging, including Flip Chip and multi-layer substrates (8+ layers). You will design, route, and stack substrates for high-performance devices, using Mentor Graphics, Cadence Allegro, and PLA.

You will collaborate with SI/PI/thermal teams and vendors to ensure manufacturability, reliability, and yield, with on-site vendor support as needed.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Materials Science, or related field.
• 5–8 years of hands-on experience in package design, focused on multi-layer substrate design.
• Proficiency with EDA tools: Mentor Graphics (Preferred), Cadence Allegro, PLA.
• Strong knowledge of substrate manufacturing and assembly rules.
• Experience with Flip Chip package design methodologies and SI/PI/thermal considerations.

Responsibilities

• Design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices.
• Package layout, routing, and stack-up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
• Ensure designs comply with substrate manufacturing and assembly rules.
• Incorporate assembly rules (die placement, bump/ball pitch, solder joint reliability).
• Develop and validate Flip Chip package designs, including RDL and underfill considerations.
• Collaborate with SI, PI, and thermal teams to ensure robust performance.
• Partner with substrate vendors and OSATs to verify manufacturability, yield, and feasibility.
• Provide on-site vendor support when required to resolve design/assembly issues.

Skills

Flip Chip design

8+ layer substrates

EDA tools

Mentor Graphics

Cadence Allegro

Substrate manufacturing rules

Assembly rules

SI/PI/thermal considerations

Vendor collaboration

Education

Bachelor’s or Master’s in Electrical Engineering / Electronics / Materials Science

Tools

Mentor Graphics

Cadence Allegro

PLA

Job description

Jora Malaysia will close on 9th September 2026. Thank you for being with us, we are cheering you on as you continue your career journey.

We are seeking a highly skilled Package Design Engineer with 5–8 years of experience in advanced IC packaging. The ideal candidate will have strong expertise in Flip Chip and multi-layer substrate (8+ layers) design, with a solid understanding of substrate manufacturing and assembly rules. The role requires close collaboration with cross-functional teams and vendors to deliver high-performance, reliable, and manufacturable package solutions.

Key Responsibilities

• Perform the design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices.
• Perform package layout, routing, and stack-up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
• Ensure designs comply with substrate manufacturing rules (trace width/spacing, via design, impedance requirements).
• Incorporate assembly rules (die placement, bump/ball pitch, solder joint reliability, warpage control) into package designs.
• Develop and validate Flip Chip package designs, including bump assignment, redistribution layers (RDL), and underfill considerations.
• Collaborate with Signal Integrity (SI), Power Integrity (PI), and thermal analysis teams to ensure robust performance.
• Partner with substrate vendors and OSATs to verify design manufacturability, yield, and assembly feasibility.
• Provide on-site vendor support when required to resolve design and assembly issues.

Skills & Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Materials Science, or related field.
• 5–8 years of hands-on experience in package design, with proven expertise in multi-layer (8+) substrate design.
• Proficiency with EDA tools: Mentor Graphics (Preferred), Cadence Allegro, PLA. (Mentor Graphics Xpedition / Cadence Allegro Package Designer)
• Strong knowledge of substrate manufacturing rules and assembly rules.
• Experience with Flip Chip package design methodologies.
• Familiarity with SI/PI/thermal considerations in advanced packages.
• Strong communication and collaboration skills for cross-functional and vendor engagement.
• Flexibility to travel and provide on-site vendor support as needed.