Flip-Chip Package Design Engineer, 8+ Layer Substrates

UST Malaysia; Bayan Lepas; On-site; MYR 120,000 - 180,000; Full time

Job summary

UST Malaysia is seeking a Package Design Engineer with 5–8 years of hands-on experience in advanced IC packaging to lead multi-layer substrate design (8+ layers) and Flip Chip methodologies. You will collaborate with SI/PI/thermal teams and vendors to ensure manufacturability and reliability.

Role requires strong expertise in Mentor Graphics, Cadence Allegro, and PLA, with travel for on-site vendor support as needed.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Electronics, Materials Science, or related field.
• 5–8 years of hands-on experience in package design.
• Experience with multi-layer (8+) substrate design.
• Proficiency with EDA tools: Mentor Graphics (Preferred), Cadence Allegro, PLA.
• Knowledge of substrate manufacturing rules and assembly rules.
• Experience with Flip Chip package design methodologies.
• SI/PI/thermal considerations in advanced packages.
• Strong communication and collaboration skills.

Responsibilities

• Design and development of multi-layer package substrates (8+ layers) for advanced semiconductor devices.
• Package layout, routing, and stack‑up planning using EDA tools (Mentor Graphics, Cadence Allegro, PLA).
• Ensure designs comply with substrate manufacturing rules (trace width/spacing, via design, impedance requirements).
• Incorporate assembly rules (die placement, bump/ball pitch, solder joint reliability, warpage control) into package designs.
• Develop and validate Flip Chip package designs, including bump assignment, redistribution layers (RDL), and underfill considerations.
• Collaborate with SI, PI, and thermal analysis teams to ensure robust performance.
• Partner with substrate vendors and OSATs to verify design manufacturability, yield, and assembly feasibility.
• Provide on-site vendor support when required to resolve design and assembly issues.

Skills

Package design

Flip Chip

EDA tools

Substrate design

Communication

Vendor collaboration

Education

Electrical Engineering / Electronics / Materials Science

Tools

Mentor Graphics

Cadence Allegro

PLA

Xpedition

Job description

UST Malaysia is seeking a Package Design Engineer with 5–8 years of hands-on experience in advanced IC packaging to lead multi-layer substrate design (8+ layers) and Flip Chip methodologies. You will collaborate with SI/PI/thermal teams and vendors to ensure manufacturability and reliability.

Role requires strong expertise in Mentor Graphics, Cadence Allegro, and PLA, with travel for on-site vendor support as needed.