FPGA/SoC Timing Engineer – Signoff & Closure

Altera; Penang; On-site; MYR 120,000 - 180,000; Full time

Job summary

Altera in Penang, Malaysia is seeking an STA design engineer specializing in timing closure for FPGA/SoC and subsystems. You will perform static timing analysis, derive interface constraints, and sign off on timing with cross-functional teams.

The role collaborates with design, architecture, and physical design teams to drive timing convergence, leveraging PVT knowledge and timing budgets to ensure robust signoff.

Qualifications

• Experience in static timing analysis and using industry-standard EDA tools like PrimeTime/PTPX.
• Good understanding of timing constraints, clocking, PVT etc.
• Tapeout experience including in latest technology 10nm or lower.
• BE/MS/Phd in Electronics/Electrical Engineering with 3+ years’ experience in physical design and timing closure/signoff.

Responsibilities

• Perform timing closure and signoff for FPGA/SoC and Subsystem timing.
• Conduct static timing analysis and derive interface timing constraints for partitions.
• Collaborate with design/architecture for timing convergence and with physical design for timing closure.

Skills

Static timing analysis

Timing constraints

Clocking

PVT

Education

Electronics/Electrical Engineering (BE/MS/PhD)

Tools

Primetime/PTPX

Job description

Altera in Penang, Malaysia is seeking an STA design engineer specializing in timing closure for FPGA/SoC and subsystems. You will perform static timing analysis, derive interface constraints, and sign off on timing with cross-functional teams.

The role collaborates with design, architecture, and physical design teams to drive timing convergence, leveraging PVT knowledge and timing budgets to ensure robust signoff.