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UST Malaysia is seeking an experienced Design Verification Engineer to develop and execute verification plans for SoC/IP designs, with hands-on experience in simulation, debugging, and functional verification. The role includes supporting emulation/FPGA-based verification and writing C/C++ test code.
Applicants should have 4+ years in design verification and strong SystemVerilog/UVM knowledge, DV methodologies, and a solid background in emulation or FPGA environments.