Digital IC Synthesis Engineer: Timing & Formal Verification

XPENG

Kuala Lumpur

On-site

MYR 180,000 - 300,000

Full time

14 days+

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Benefits offered by this job

Competitive salary
Pension benefits
Growth opportunities
Global projects

Job summary

XPENG in Malaysia seeks a skilled IC design engineer focused on logic synthesis, formal verification, and SDC management. You will optimize timing, area and power, and work with front‑end, back‑end and DFT teams to drive robust timing closure.

Requirements include a Master’s/PhD in Microelectronics or related fields, strong knowledge of Verilog/SystemVerilog, Linux, and scripting (Tcl/Python). XPENG offers a competitive package, pension benefits, and growth opportunities across Europe.

Qualifications

  • Hold a Master's or Doctoral degree in Microelectronics, Integrated Circuit Engineering, Electronic Engineering, Computer Science or related disciplines.
  • Solid digital circuit fundamentals and CMOS device principles.
  • Experience with Verilog/SystemVerilog and Linux; scripting skills in Python/Tcl are a plus.

Responsibilities

  • Conduct logic synthesis at block and chip level using Synopsys DC/FC and Cadence Genus.
  • Optimize timing, area and power with customized synthesis strategies.
  • Resolve setup/hold and CDC timing closures.
  • Perform formal verification with LEC using Formality, Conformal and other tools.
  • Create precise SDC files to standardize STA and flows.
  • Collaborate with front-end, DFT and physical teams to boost synthesizability and fix timing bottlenecks.

Skills

Verilog & SystemVerilog
Linux
Scripting (Python/Tcl)

Education

Master's or PhD in Microelectronics / IC Engineering

Job description

XPENG in Malaysia seeks a skilled IC design engineer focused on logic synthesis, formal verification, and SDC management. You will optimize timing, area and power, and work with front‑end, back‑end and DFT teams to drive robust timing closure.

Requirements include a Master’s/PhD in Microelectronics or related fields, strong knowledge of Verilog/SystemVerilog, Linux, and scripting (Tcl/Python). XPENG offers a competitive package, pension benefits, and growth opportunities across Europe.

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