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XPENG in Malaysia seeks a skilled IC design engineer focused on logic synthesis, formal verification, and SDC management. You will optimize timing, area and power, and work with front‑end, back‑end and DFT teams to drive robust timing closure.
Requirements include a Master’s/PhD in Microelectronics or related fields, strong knowledge of Verilog/SystemVerilog, Linux, and scripting (Tcl/Python). XPENG offers a competitive package, pension benefits, and growth opportunities across Europe.
XPENG in Malaysia seeks a skilled IC design engineer focused on logic synthesis, formal verification, and SDC management. You will optimize timing, area and power, and work with front‑end, back‑end and DFT teams to drive robust timing closure.
Requirements include a Master’s/PhD in Microelectronics or related fields, strong knowledge of Verilog/SystemVerilog, Linux, and scripting (Tcl/Python). XPENG offers a competitive package, pension benefits, and growth opportunities across Europe.