Digital Design Engineer (SOC/IP)

XINPAL (MALAYSIA) SDN. BHD.; Bayan Lepas; On-site; MYR 90,000 - 130,000; Full time

Job summary

XinPal Malaysia seeks a Digital Design Engineer (SoC/IP) in Bayan Lepas, Penang to drive hardware IP development from concept to RTL and final SoC integration. You will collaborate with Architecture, Physical Design, and DV to hit PPA targets and timing constraints.

The role requires a minimum of 2 years' experience in Digital IC/RTL Design and hands-on RTL coding with a strong background in CPU architectures, AMBA protocols, and high-speed interfaces.

Qualifications

• Bachelor's or Master's degree in Electrical & Electronics Engineering or Computer Engineering.
• Minimum 2 years of Digital IC / RTL Design experience.
• Experience delivering digital IPs from spec to RTL.

Responsibilities

• Lead hardware IP/module development from scratch to SoC integration.
• Derive micro-architecture design specs from system requirements.
• Collaborate with Architecture, Physical Design, and DV teams to meet PPA and timing targets.
• Perform RTL coding, generate timing constraints (SDC), and implement UPF-based low‑power designs.

Skills

RTL Design

CPU Architecture

AMBA Protocols

High‑speed Interfaces

Pre-silicon Simulation

Post-silicon Debug

Pipelining

Timing Optimization

Education

Electrical & Electronics Engineering

Computer Engineering

Job description

XinPal Malaysia is part of an MNC headquartered in Singapore, specializing in delivering innovative technology solutions and supporting cutting‑edge semiconductor projects. We are committed to building a high-performing team through innovation, collaboration, and continuous growth opportunities.

We are looking for a Digital Design Engineer (SoC/IP) in Bayan Lepas, Penang to lead the development of hardware IP and digital modules for advanced SoC solutions. The role involves driving the design lifecycle from micro‑architecture definition and RTL development to SoC integration, while collaborating closely with Architecture, Physical Design, and Design Verification teams to achieve performance, power, area (PPA), and timing targets. You will also be responsible for RTL coding, timing constraint (SDC) generation, and implementing low‑power designs using UPF to deliver high‑quality semiconductor products.

Lead and drive hardware IP/module development from scratch—spanning from initial concept, micro‑architecture definition, to robust RTL coding and final SoC integration.

Derive hardware micro‑architecture design specifications from system‑level requirements and author comprehensive hardware functional specs / feature lists.

Partner closely with Architecture, Physical Design (Backend), and Design Verification (DV) teams to ensure the design meets strict PPA (Performance, Power, Area) and timing targets.

Responsible for robust RTL coding, SDC (Timing Constraints) generation, and low‑power design implementation using UPF.

Bachelor's or Master's Degree in Electrical & Electronics Engineering, Computer Engineering, or a related field.

Minimum 2 years of experience in Digital IC / RTL Design.

Proven experience in designing and delivering digital IPs from specification to verified RTL.

Strong knowledge of one or more of the following:

CPU architecture, AMBA protocols (AXI/CHI/ACE), and cache coherency.

High-speed digital design, including pipelining and timing optimization.

High-speed interfaces such as DDR, PCIe, USB, UCIe, or CXL.

Experience with pre-silicon simulation and post-silicon bring‑up/debugging is an advantage.