Synthesis & STA Engineer — ASIC/SoC Timing Expert

Pride Global; Seberang Perai; On-site; MYR 123,000 - 201,000; Full time

Job summary

Pride Global in Malaysia is seeking an experienced Synthesis & STA Engineer to support ASIC/SoC design projects. The role focuses on RTL synthesis, static timing analysis, timing closure, and design optimization to meet PPA objectives.

You will collaborate with RTL, Physical Design, and DFT teams to identify timing issues, optimize performance, and ensure timing requirements across the design flow. Strong Verilog/SystemVerilog and TCL scripting are essential, with experience in Synopsys tools

Qualifications

• Bachelor's or Master's degree in Electrical or related field.
• 4-10 years in ASIC/SoC design, RTL synthesis or STA.
• Strong hands-on RTL synthesis and STA methods.
• Proficient in Verilog/SystemVerilog and digital design fundamentals.
• Experience with Synopsys tools and timing constraints.

Responsibilities

• Perform RTL synthesis to create optimized gate-level netlists.
• Develop and optimize synthesis scripts and timing constraints.
• Conduct STA including setup/hold/recovery checks and timing reports.
• Identify critical paths and timing violations; propose fixes.
• Collaborate with RTL, Physical Design, and DFT teams to resolve timing issues.
• Create and maintain SDC files for accurate timing analysis.
• Optimize designs to meet frequency, power, and area targets.
• Support timing closure across pre-layout and post-layout stages.
• Analyze clock domains, false paths, multicycle paths, and CDC issues.
• Assist timing signoff and use EDA tools to improve timing performance.
• Help engineering teams identify optimization opportunities in the ASIC/SoC flow.

Skills

RTL synthesis

Static timing analysis

Verilog/SystemVerilog

Tcl scripting

Debugging / problem solving

Cross-functional collaboration

Education

Bachelor's or Master's degree in Electrical Engineering

Tools

Synopsys Design Compiler

Fusion Compiler

PrimeTime

SDC (constraints)

Job description

Pride Global in Malaysia is seeking an experienced Synthesis & STA Engineer to support ASIC/SoC design projects. The role focuses on RTL synthesis, static timing analysis, timing closure, and design optimization to meet PPA objectives.

You will collaborate with RTL, Physical Design, and DFT teams to identify timing issues, optimize performance, and ensure timing requirements across the design flow. Strong Verilog/SystemVerilog and TCL scripting are essential, with experience in Synopsys tools