Turing Chip Project- Digital IC Synthesis Implementation Engineer

XPENG; Kuala Lumpur; Vor Ort; MYR 180.000 - 300.000; Vollzeit

Benefits dieser Stelle

Competitive salary

Pension benefits

Growth opportunities

Global projects

Zusammenfassung

XPENG in Malaysia seeks a skilled IC design engineer focused on logic synthesis, formal verification, and SDC management. You will optimize timing, area and power, and work with front‑end, back‑end and DFT teams to drive robust timing closure.

Requirements include a Master’s/PhD in Microelectronics or related fields, strong knowledge of Verilog/SystemVerilog, Linux, and scripting (Tcl/Python). XPENG offers a competitive package, pension benefits, and growth opportunities across Europe.

Qualifikationen

• Hold a Master's or Doctoral degree in Microelectronics, Integrated Circuit Engineering, Electronic Engineering, Computer Science or related disciplines.
• Solid digital circuit fundamentals and CMOS device principles.
• Experience with Verilog/SystemVerilog and Linux; scripting skills in Python/Tcl are a plus.

Aufgaben

• Conduct logic synthesis at block and chip level using Synopsys DC/FC and Cadence Genus.
• Optimize timing, area and power with customized synthesis strategies.
• Resolve setup/hold and CDC timing closures.
• Perform formal verification with LEC using Formality, Conformal and other tools.
• Create precise SDC files to standardize STA and flows.
• Collaborate with front-end, DFT and physical teams to boost synthesizability and fix timing bottlenecks.

Kenntnisse

Verilog & SystemVerilog

Linux

Scripting (Python/Tcl)

Ausbildung

Master's or PhD in Microelectronics / IC Engineering

Jobbeschreibung

Job Responsibilities

Logic Synthesis & Optimization

• 1.Conduct complex-level and chip-level logic synthesis utilizing mainstream EDA tools, including Synopsys DC/FC and Cadence Genus.
• 2.Formulate and implement customized synthesis strategies to optimize performance across timing, area and power consumption.
• 3.Analyze setup and hold time violations, and independently troubleshoot and resolve complex clock domain crossing (CDC) issues to ensure robust timing closure.

Formal Verification

• 1.Perform logic equivalence check (LEC) between RTL and gate-level netlists via Formality, Conformal and other formal verification tools, ensuring full functional consistency throughout the synthesis process.

SDC Development & Management

• 1.Develop precise, comprehensive and scalable SDC files to standardize and guide subsequent physical implementation and static timing analysis (STA) flows

Cross-team Collaboration

• 1.Collaborate closely with front-end design engineers and DFT engineers to fully comprehend design specifications and deliver professional design-for-synthesis suggestions to improve design synthesizability.
• 2.Cooperate with physical design teams to analyze and resolve critical timing bottlenecks and key implementation issues.

Job Requirements

Mandatory Requirements

Education & Major

• 1.Hold a Master's or Doctoral degree in Microelectronics, Integrated Circuit Engineering, Electronic Engineering, Computer Science or other related technical disciplines.

Professional Knowledge

• 1.Possess solid digital circuit fundamentals and in-depth mastery of CMOS device principles, complete timing analysis theories (covering setup/hold time, clock jitter, clock skew, etc.), as well as low-power design methodologies.

Tools & Programming Skills

• 1.Proficient in digital design languages including Verilog and SystemVerilog.
• 2.Familiar with Linux operating environment and skilled in at least one scripting language (Tcl / Perl / Python / Shell) for automated flow development and design debugging.

Design Flow Competency

• 1.Have a clear understanding of the end-to-end digital IC design flow from front-end RTL development to back-end physical implementation, with a solid grasp of core mid-end design procedures.

Personal Competencies

• 1.Equipped with strong analytical thinking and independent problem-solving capabilities, rigorous and meticulous working style, as well as excellent cross-team communication and collaborative skills.

Preferred Qualifications

• 1.Hands-on project experience in IC mid-end or back-end implementation based on mainstream advanced process nodes (28nm, 12nm, 7nm, etc.).
• 2.Practical engineering experience in UPF-based low-power design and implementation flows.
• 3.In-depth academic research or project experience focusing on formal verification, logic synthesis, or static timing analysis (STA).

XPENG offers:

• An interesting, unique and very varied job at XPENG
• A job with an incredibly large contact surface both internally and externally
• An attractive salary package incl. pension and with the possibility of a bonus
• To be involved in the growth of an existing EV brand in Europe

Next steps:

For more information on how we process your personal data, please see: https://www.xpeng.com/policy

As part of our application process, certain positions at our company require a pre-employment screening to ensure the reliability and integrity of our employees. This screening is a standard procedure and may include components such as a Criminal Background Check from your current or previous country of residence over the past five years. Additionally, the process may involve an integrity questionnaire, verification of identification, diplomas, work experience, and consultation of the central insolvency register.

We appreciate your understanding and cooperation in this important matter, as it helps us maintain the high standards expected by our team.

Our Commitment to Diversity and Inclusion:

At XPENG, we're an equal-opportunity employer that values diversity and positively encourages applications from suitably qualified and eligible candidates regardless of race, religion, sex, national origin, gender, sexual orientation, age, marital status, disability status or other applicable legally protected characteristics.